Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi,

I have a custom board with
1) MityDspl-138F module (with FPGA)
2) No Ethernet port
3) UART,USB,SD CARD interface
4) We are using ADC5560 and DAC5672, reference is taken from Analog Expansion Board.
ADC and DAC both operates on 40MHz.
5) we have used uPP interface in our end application.

we have done following steps till date.

1) I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.

2) Invidually tested ADC and DAC examples. Also,we build and tested Real time ADC to DAC data transfer at frequencies greater than 5KHz.

I have following problems.

#1. In real time ADC to DAC data transfer, we are not getting proper output waveforms on DAC for lower frequencies(lower than 5KHz).
We need to even output low frequencies as low as 5Hz in our end application. Please provide some suggestion about this.

#2. We are giving modulated input waveform with 10.7 MHZ carrier and FM frequency varies from 5Hz to 20KHz. To demodulate the signal,We do decimation and other
processing to get FM signal and then giving it to DAC but we are not getting desired output. Please provide suggestions.

#3. In DAC test example provided by CL, sine wave is generated on the based of 40MHz sampling frequency of the FPGA. We tried DAC test example to generate sine wave on
the based of 156250 Hz sampling frequency and also made necessary changes in FPGA code to get 156250 Hz for DAC clock input. We did so, as we required this sampling
rate in our end application. The problem is in that case we are not able to get desired output for signal frequency. So, we wanted to know that is there any relation
between DAC clock and sine wave generated output from DSP.

Thanks and Regards,
Vivek Ponnani