Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

For which module? One that includes an FPGA or not?

The one without the FPGA.

This is the mainquestion: Are there some not used Pins of the EMA interface which i can use as GPIO and keep the onboard memory working at the same time?
I need the GPIOs on the EMA-Pins, because i wanna connect some devices to the dev-baord and the EMA-interface is completely outrouted to the expansionheaders.

Yes, there should be several.

The only interface on the EMA on the modules with non-FPGA pins is the NAND (x8, but the upper 8 bit lines should probably be left alone). The NAND interface uses the following signals:

EMA_D(15..0)
EMA_WAIT0
EMA_OE
EMA_CS3
EMA_A(2..1)
EMA_WE

All of the other EMA lines that are brought to the edge connector should be free to use, including the EMA_A(13..3), EMA_CS(5,4) and the EMA SDRAM control signals (EMA_RAS/EMA_CAS, etc.).

-Mike

In the case of the Industrial IO board though, pins 197 through 200 are tied directly to 3.3V for the VCCO_[0,1] bank connections to the FPGA. These correspond to:

197    O    EMA_A_RW
199    O    EMA_CS[3]
198    I    EMA_WAIT[0]
200    I    EMA_WAIT[1]

I understand that the CL wiki says it may be done (with certain caveats) but I wanted to make sure before doing it myself on my own design (which probably has to work on both L138 and L138F just in case. The trials of an engineer!). Maybe I should connect pins 197 and 200 to Vcc and leave 199,198 floating and then reassign EMA_A_RW and EMA_WAIT¹ muxes? At worst I can jumper it (actually, that sounds nicer) but I thought I'd ask.

Thanks,
Conor.

Hi Conor,

On the Non-FPGA modules, all 4 of these signals have a 1K Ohm series resistor between the on-board nets and the edge connector. This effectively makes putting a non FPGA module into a board like the Industrial I/O kit OK if you are using 3.3V Bank I/O (it effectively adds a 1 K pull up onto the nets, which is a bit strong, but is OK as these nets should be driven if used for these functions). However, it does have an effect on the external edge rate of the lines if you want to drive (or externally drive) these output (input) nets.

I just checked the specification, and these 1K series resistors are definitely not listed / described. We'll have to update this. Very sorry for the confusion.

The bigger issue with using a non-FPGA module on the Industrial I/O board is that the EMIF address and data lines get a bunch of stubs added to them as those lines are routed around on the baseboard for FPGA features. We've tested this configuration, and as is mentioned on the wiki page it seems OK unless you get down to colder temperatures.

-Mike

That's great Mike - exactly what I hoped to hear

I was wondering if you had done precisely this given that the wiki said the non-FPGA modules would work. But I have an L138F here not an L138 so couldn't really check it myself and wasn't about to commit either way.

I wouldn't really expect that information to be part of the specification but it's handy to have a note in the wiki about it. I did wonder why CS3 is brought to the edge connector as it's used internally but then again, all the other chip selects are so why not. Besides, it can't be easy making a board that will work with two feature sets.

Conor.