Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hi Jonas,

From looking at your boot log it looks like the kernel incorrectly found a PHY at address 31, where it should of found it at address 3. This could be caused by the kernel or u-boot not taking the PHY out of reset.

In our reference design we have the kernel take the phy out of reset with the following device tree node (socfpga_mitysom5csx_devkit.dts):

&gmac1 {
    status = "okay";
    phy-mode = "rgmii";

    txd0-skew-ps = <0>;
    txd1-skew-ps = <0>;
    txd2-skew-ps = <0>;
    txd3-skew-ps = <0>;
    rxd0-skew-ps = <420>;
    rxd1-skew-ps = <420>;
    rxd2-skew-ps = <420>;
    rxd3-skew-ps = <420>;
    txen-skew-ps = <0>;
    txc-skew-ps = <1860>;
    rxdv-skew-ps = <420>;
    rxc-skew-ps = <1680>;

    max-frame-size = <3800>;

    snps,reset-delays-us = <0 10000 1000000>;
    snps,reset-gpio = <&porta 28 1>;             
    snps,reset-active-low;
};

The snps,reset-gpio element is telling the kernel which reset to use. Please note that our reference uses the 4.9 kernel, where you are using the 5.8 kernel so the syntax might have changed.

Dan

Hey Dan,

thanks for the reply.

I created my dts with the sopc2dts tool, but appended the information given in your example, which currently does not seem to help.

Before that i already got it running roughly by calling ethtool -s eth0 speed 10 duplex full autoneg off, basically forcing the interface to use the lowest possible speed. Due to this working (but also intermittingly failing), I am suspecting
the clock skews are either configured wrong or not configured at all (i tried to read out the clock skews of the mmd registers in the micrelksz9031 chip, and they do not seem correct, but it's hard to tell).

You also mentioned an unexpected PHY address, what could be the reason for that, how could i check that? Could that be related to a wrong configuration of the clock skews?

Here is my (modified) device tree node:

        hps_0_gmac1: ethernet@0xff702000 {
            compatible = "synopsrstmgrys,dwmac-20.1", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
            reg = <0xff702000 0x00002000>;
            interrupt-parent = <&hps_0_arm_gic_0>;
            interrupts = <0 120 4>;
            clocks = <&emac1_clk>;
            clock-names = "stmmaceth";    /* embeddedsw.dts.params.clock-names type STRING */
            interrupt-names = "macirq";    /* embeddedsw.dts.params.interrupt-names type STRING */
            rx-fifo-depth = <4096>;    /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
            snps,multicast-filter-bins = <256>;    /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
            snps,perfect-filter-entries = <128>;    /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
            status = "okay";    /* embeddedsw.dts.params.status type STRING */
            tx-fifo-depth = <4096>;    /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
            address-bits = <48>;
            max-frame-size = <3800>;    /* appended from boardinfo */
            local-mac-address = [08 15 ba de af fe];
            phy-mode = "rgmii";    /* appended from boardinfo */
            phy-addr = <0x1f>;    /* appended from boardinfo */
            txd0-skew-ps = <0>;
            txd1-skew-ps = <0>;
            txd2-skew-ps = <0>;
            txd3-skew-ps = <0>;
            rxd0-skew-ps = <420>;
            rxd1-skew-ps = <420>;
            rxd2-skew-ps = <420>;
            rxd3-skew-ps = <420>;
            txen-skew-ps = <0>;
            txc-skew-ps = <1860>;
            rxdv-skew-ps = <420>;
            rxc-skew-ps = <1680>;
            altr,sysmgr-syscon = <&hps_0_sysmgr 0x00000060 2>;    /* appended from boardinfo */
            reset-names = "stmmaceth";    /* appended from boardinfo */
            resets = <&hps_0_rstmgr 33>;    /* appended from boardinfo */
            reset-delays-us = <0 10000 1000000>;
            reset-gpio = <&hps_0_gpio1_porta 28 1>; 
            reset-active-low;
        }; //end ethernet@0xff702000 (hps_0_gmac1)

Thanks for the help!

Jonas

I apparently used the wrong gpio port, now the reset seems to be working correctly (ethtool shows a PHYAD of 3), but unfortunately i still can't get a higher speed than 10Mbs with sometimes high packet losses.

Jonas

Hi Jonas,

You might not have the phy driver built into your kernel, so the phy skews aren't being set. I believe the config is: CONFIG_MICREL_PHY.

Dan

Hey Dan,

I checked the kernel configuration in menuconfig and directly in the .config of my kernel and the config was enabled.
Also it seems like the device is detected properly and the correct driver is chosen:

[    1.567200] Micrel KSZ9031 Gigabit PHY stmmac-0:03: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=stmmac-0:03, irq=POLL)

and

Configuring network interfaces... [   19.500625] socfpga-dwmac ff702000.ethernet eth0: PHY [stmmac-0:03] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)

I still have the feeling it's something in the device tree, is there something special to configure in Quartus besides the Pin Configuration?

Jonas

Hi Jonas,

Looking at the device-tree binding doc for the phy it looks like if you specify the phy address you need to put the skews in their own phy node instead of in the MAC node. Take a look at the example here: https://support.criticallink.com/gitweb/?p=linux-socfpga.git;a=blob;f=Documentation/devicetree/bindings/net/micrel-ksz90x1.txt;h=a35558cf3af66b97de28fa61822fcd9021ea1177;hb=refs/heads/socfpga-4.9.78-ltsi

I looked in the 5.8 bindings doc for the phy and they removed the example of the autodetect phy, I'm not sure why.

I would recommend removing the phy-addr line from your dts, which should cause it to autodetect the phy and would match the example in the 4.9 bindings doc.

Dan

Hey Dan,
I tried the device tree configurations you mentioned and also the generic ones adapted to my hardware from
https://elixir.bootlin.com/linux/v5.8.18/source/Documentation/devicetree/bindings/net
(also your example is listed there under micrel), but to no avail.
I also tried removing the phy-addr line, which didn't change the behaviour for me. I also now tried to set the timing skews on bootup (in the boot script), but i am guessing in between there is another reset anyway. I also further confirmed, that the correct micrel driver is on the device and also used:

root@cyclone5:/sys/bus/mdio_bus/drivers/Micrel KSZ9031 Gigabit PHY# ls
bind  stmmac-0:03  uevent  unbind

I also compared my device to your device tree, which you posted in your first reply, also considering the other part of the emac in socfpga.dtsi (included down the line in your devicetree):

        gmac1: ethernet@ff702000 {
            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
            altr,sysmgr-syscon = <&sysmgr 0x60 2>;
            reg = <0xff702000 0x2000>;
            interrupts = <0 120 4>;
            interrupt-names = "macirq";
            mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
            clocks = <&emac_1_clk>;
            clock-names = "stmmaceth";
            resets = <&rst EMAC1_RESET>;
            reset-names = "stmmaceth";
            snps,multicast-filter-bins = <256>;
            snps,perfect-filter-entries = <128>;
            tx-fifo-depth = <4096>;
            rx-fifo-depth = <4096>;
            status = "disabled";
        };

To me they also look pretty similar.
I also tried to check the clocks, at least how they are configured in quartus and that also seemed okay.

One thing, which I should've tried much earlier, is, running your provided image, which also doesn't seem to work besides the 10Mbps, which now leads me to think it's a hardware issue or an issue in the router.

I will update, if I find anything new. Thanks for the help!

Regards
Jonas

Okay an update:

Skews are set correctly, I read them out with [[ https://github.com/wkz/phytool ]] and could confirm the values set in the device tree after kernel boot.
I measured the clock GTX_CLK, supplied from the MAC to the PHY. It starts out at 125 MHz (which is configured in Quartus), but after "Configuring network interfaces" it falls back to 2.5MHz, which is not fit for more than 10Mbps.
The RX_CLK, which is generated by the KSZ9031 based on the GTX_CLK (with an internal PLL), produces an 125MHz Signal (or 25 or 2.5, depending on what I set it with ethtool).

So the current suspect is the GTX_CLK or whatever controls it, do you have any idea regarding that?

Regards
Jonas

Hi Jonas,

If you are also witnessing this issue with our stock SD card image then it sounds like there could be a hardware problem with dev kit. Could you provide me the serial number of both the SOM and baseboard?

The serial numbers are on white stickers that have QR codes on them. The serial number is the second line and should look something like 19039000.

The SOM serial number is on the back of the SOM.
The baseboard serial number should be on the top of the baseboard by the partial HSMC connector.

Thank you,
Dan

Sure,

Baseboard: 1701 8998
SoM: 1803 5616

It's an 5CSX-H6-42A-RC Module

Regards
Jonas

Hi Jonas,

Thank you for providing the serial numbers. I've double checked our production logs and that development kit did link up at 1Gbps speeds and was able to send and receive ethernet packets before shipping out.

Can you boot again using the reference SD card and post a console log of the following:

• Boot up
• ethtool of eth0
• pinging a device on your network

Reference SD card image: https://support.criticallink.com/redmine/attachments/download/27161/sdcard_5csx_h6_42a_20201116.zip

Also just to double check have you tried connecting up another device instead of the dev kit using the same ethernet cable/end point and check if that device links up and works at 1Gbps? I'm guessing this was part of your debugging of your router but I just wanted to double check.

Regards,
Dan

Hi Dan,

my plan was to take the board home over the weekend to test out a different router, in the office i tested with 2 different cables and 2 different router plugs, which worked fine for 100Mbps at least (only confirmed it with a quick speed test).

Bootup:

U-Boot SPL 2013.01.01 (Nov 17 2020 - 00:43:58)
BOARD : Critical Link MitySOM-5CSx Module
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: COLD
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: Initializing SDRAM ECC
SDRAM: ECC initialized successfully with 1554 ms
SDRAM: ECC Enabled
ALTERA DWMMC: 0

U-Boot 2013.01.01 (Nov 17 2020 - 00:44:13) Critical Link MitySOM-5CSx

CPU   : Altera SOCFPGA Platform
BOARD : Critical Link MitySOM-5CSx Module
I2C:   ready
DRAM:  1 GiB
MMC:   ALTERA DWMMC: 0
In:    serial
Out:   serial
Err:   serial
Info - Didn't find block
Net:   mii0
gpio: pin 0 (bank/mask = 0/0x00000001)
gpio: pin 0 (gpio 0) value is 1
Hit any key to stop autoboot:  0 
4078608 bytes read in 223 ms (17.4 MiB/s)
21795 bytes read in 30 ms (709 KiB/s)
reading /dev_5cs.rbf
7007204 bytes read in 325 ms (20.6 MiB/s)
## Starting application at 0x3FF76598 ...
## Application terminated, rc = 0x0
## Starting application at 0x3FF76598 ...
## Application terminated, rc = 0x0
## Flattened Device Tree blob at 00000100
   Booting using the fdt blob at 0x00000100
   Loading Device Tree to 03ff7000, end 03fff522 ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.9.78-ltsi-yocto-standard (oe-user@oe-host) (gcc version 7.3.0 (GCC) ) #1 SMP Mon Nov 16 22:09:17 UTC 2020
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: MitySOM-5CSX Altera SOCFPGA Cyclone V
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @bf7ca000 s26764 r8192 d22388 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260096
Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p3 rw rootwait
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1029524K/1048576K available (6144K kernel code, 445K rwdata, 1392K rodata, 1024K init, 153K bss, 19052K reserved, 0K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xc0800000 - 0xff800000   (1008 MB)
    lowmem  : 0x80000000 - 0xc0000000   (1024 MB)
    pkmap   : 0x7fe00000 - 0x80000000   (   2 MB)
    modules : 0x7f000000 - 0x7fe00000   (  14 MB)
      .text : 0x80008000 - 0x80700000   (7136 kB)
      .init : 0x80900000 - 0x80a00000   (1024 kB)
      .data : 0x80a00000 - 0x80a6f76c   ( 446 kB)
       .bss : 0x80a6f76c - 0x80a95da4   ( 154 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
    Build-time adjustment of leaf fanout to 32.
NR_IRQS:16 nr_irqs:16 16
L2C: DT/platform modifies aux control register: 0x02060000 -> 0x02460000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410030c9, AUX_CTRL 0x76460001
GIC: PPI13 is secure or misconfigured
GIC: PPI13 is secure or misconfigured
clocksource: timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns
Switching to timer-based delay loop, resolution 10ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=1000000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
ftrace: allocating 21441 entries in 63 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100058
GIC: PPI13 is secure or misconfigured
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (400.00 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
fpga-region soc:base-fpga-region: FPGA Region probed
clocksource: Switched to clocksource timer1
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
workingset: timestamp_bits=30 max_order=18 bucket_order=0
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
ntfs: driver 2.1.32 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
io scheduler noop registered (default)
dma-pl330 ffe01000.pdma: Loaded driver for PL330 DMAC-341330
dma-pl330 ffe01000.pdma:     DBUFF-512x8bytes Num_Chans-8 Num_Peri-32 Num_Events-8
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
console [ttyS0] disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 45, base_baud = 6250000) is a 16550A
console [ttyS0] enabled
brd: module loaded
at24 0-0050: 2048 byte 24c16 EEPROM, writable, 1 bytes/write
cadence-qspi ff705000.spi: n25q128a11 (16384 Kbytes)
6 ofpart partitions found on MTD device ff705000.spi.0
Creating 6 MTD partitions on "ff705000.spi.0":
0x000000000000-0x000000040000 : "Preloader Image 0-3" 
0x000000040000-0x000000050000 : "U-Boot Env" 
0x000000050000-0x000000060000 : "DTB" 
0x000000060000-0x0000000e0000 : "U-Boot" 
0x0000000e0000-0x0000008e0000 : "Kernel" 
0x0000008e0000-0x000001000000 : "FPGA" 
cadence-qspi ff705000.spi: n25q128a11 (16384 Kbytes)
1 ofpart partitions found on MTD device ff705000.spi.1
Creating 1 MTD partitions on "ff705000.spi.1":
0x000000000000-0x000001000000 : "Data" 
libphy: Fixed MDIO Bus: probed
CAN device driver interface
c_can_platform ffc00000.can: c_can_platform device registered (regs=c08eb000, irq=26)
c_can_platform ffc01000.can: c_can_platform device registered (regs=c08ed000, irq=30)
stmmac - user ID: 0x10, Synopsys ID: 0x37
 Ring mode enabled
 DMA HW capability register supported Enhanced/Alternate descriptors
    Enabled extended descriptors
 RX Checksum Offload Engine supported
    COE Type 2
 TX Checksum insertion supported
 Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth%d: PHY ID 00221622 at 3 IRQ POLL (stmmac-0:03) active
dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRAM
dwc2 ffb40000.usb: DWC OTG Controller
dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1
dwc2 ffb40000.usb: irq 47, io mem 0x00000000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: DWC OTG Controller
usb usb1: Manufacturer: Linux 4.9.78-ltsi-yocto-standard dwc2_hsotg
usb usb1: SerialNumber: ffb40000.usb
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
rtc-abx80x 0-0069: model 1805, revision 2.3, lot e, wafer 11, uid 1ad0
rtc-abx80x 0-0069: rtc core: registered abx8xx as rtc0
i2c /dev entries driver
lm73 0-004c: sensor 'lm73'
EDAC MC0: Giving out device to module altera_edac controller soc:sdramedac: DEV soc:sdramedac (INTERRUPT)
Synopsys Designware Multimedia Card Interface Driver
dw_mmc ff704000.dwmmc0: IDMAC supports 32-bit address mode.
dw_mmc ff704000.dwmmc0: Using internal DMA controller.
dw_mmc ff704000.dwmmc0: Version ID is 240a
dw_mmc ff704000.dwmmc0: DW MMC controller at irq 39,32 bit host data width,1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dw_mmc ff704000.dwmmc0: 1 slots initialized
lp5562 0-0030: internal clock used
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Altera SOCFPGA FPGA Manager registered
altera_hps2fpga_bridge ff400000.fpga_bridge: fpga bridge [lwhps2fpga] registered
altera_hps2fpga_bridge ff500000.fpga_bridge: fpga bridge [hps2fpga] registered
oprofile: no performance counters
oprofile: using timer interrupt.
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20161123 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
input: gpio_keys as /devices/platform/gpio_keys/input/input0
ttyS0 - failed to request DMA
Waiting for root device /dev/mmcblk0p3...
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
mmc0: new high speed SDHC card at address aaaa
mmcblk0: mmc0:aaaa SB32G 29.7 GiB 
 mmcblk0: p1 p2 p3
EXT4-fs (mmcblk0p3): mounting ext3 file system using the ext4 subsystem
random: fast init done
EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext3 filesystem) on device 179:3.
devtmpfs: mounted
Freeing unused kernel memory: 1024K
INIT: version 2.88 booting
Starting udev
udevd[82]: starting version 3.2.2
udevd[83]: starting eudev-3.2.2
EXT4-fs (mmcblk0p3): re-mounted. Opts: (null)
INIT: Entering runlevel: 5
Configuring network interfaces... socfpga-dwmac ff702000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
socfpga-dwmac ff702000.ethernet eth0: registered PTP clock
udhcpc (v1.24.1) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
done.
Starting system message bus: dbus.
Starting OpenBSD Secure Shell server: sshd
  generating ssh RSA key...
  generating ssh ECDSA key...
  generating ssh DSA key...
  generating ssh ED25519 key...
random: crng init done
NET: Registered protocol family 10
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
done.
Starting rpcbind daemon...done.
starting statd: done
Starting atd: OK
exportfs: can't open /etc/exports for reading
NFS daemon support not enabled in kernel
loading RTC calibration values from /etc/abrtc.cal ...
Starting system log daemon...0
Starting kernel log daemon...0
Starting crond: OK
Starting Network Interface Plugging Daemon: eth0.
Starting tcf-agent: OK

Poky (Yocto Project Reference Distro) 2.4.4 mitysom-c5 /dev/ttyS0

mitysom-c5 login: root

Ethtool and ping:

root@mitysom-c5:~# ethtool eth0
Settings for eth0:
    Supported ports: [ TP MII ]
    Supported link modes:   10baseT/Half 10baseT/Full 
                            100baseT/Half 100baseT/Full 
                            1000baseT/Half 1000baseT/Full 
    Supported pause frame use: Symmetric Receive-only
    Supports auto-negotiation: Yes
    Advertised link modes:  10baseT/Half 10baseT/Full 
                            100baseT/Half 100baseT/Full 
                            1000baseT/Half 1000baseT/Full 
    Advertised pause frame use: No
    Advertised auto-negotiation: Yes
    Speed: 10Mb/s
    Duplex: Half
    Port: MII
    PHYAD: 3
    Transceiver: external
    Auto-negotiation: on
    Supports Wake-on: d
    Wake-on: d
    Current message level: 0x0000003f (63)
                   drv probe link timer ifdown ifup
    Link detected: no
root@mitysom-c5:~# ping 192.168.3.1
connect: Network is unreachable

Forcing it again on 10Mbps, will make it work. Forcing it on more than that, and it won't.

root@mitysom-c5:~# ethtool -s eth0 speed 10 duplex full autoneg off
root@mitysom-c5:~# socfpga-dwmac ff702000.ethernet eth0: Link is Up - 10Mbps/Full - flow control off
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
ethtool -s eth0 speed 100 duplex full autoneg off
root@mitysom-c5:~# socfpga-dwmac ff702000.ethernet eth0: Link is Down

Regards
Jonas

I also tried it at home now (with your image) and I can reproduce the same behavior. So it points directly towards the hardware. Are there some hardware configurations, which might affect the behavior, e.g. the CSEL switches?

Regards
Jonas

Hi Jonas,

The CSEL switches shouldn't have an effect on the ethernet interface, they are more used during the early boot process.

It sounds to me like there is a hardware defect with the development kit. Someone will contact you via email on processing an RMA for that board.

Best regards,
Dan

Hey Dan,

I just received the new board and ethernet worked instantly without any problems!
Thanks again for the help.

Regards Jonas

Hi Jonas,

Awesome, I'm glad to hear it!

Best regards,
Dan