Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hey all,

I've got another weird problem coming up.
For a few days now, especially when the board is in operation for a longer period of time, I have noticed that the data transfer from the FPGA DDR, with a DMA instantiated in the FPGA, via the f2h bridge to the HPS DDR is doing something unexpected.

Instead of the last two values 62
and 0 at the end of the read data, they are at the beginning. The
2 elements read at the beginning are those from a previous run, so if the previous last values were 11 12, they would
appear instead of the 62 0. It seems that this data is still in some pipeline/FIFO and is not read appropriately on the previous run.

I used Signal Tap to verify the signals up to the final logic,
which is then connected to the bridge, and the data looks fine.

My current theory is that too high a frequency has been chosen for the design and this is causing errors.
A higher temperature then exacerbates the problem. Letting the board cool down removes the problem
for a period of time.

However, nothing was changed on the DMA itself and it was working fine before. And the error seems too uniform, if the frequency is too high, I would expect more data corruption
than just a shift. Also, it doesn't seem to happen on the FPGA side.

Do you have any additional ideas/tips/debugging strategies?

Result
62 0 0 50 44 17 15 37
35 40 77 0 49 21 62 27
56 44 57 24 0 28 26 48
36 11 68 36 29 0 55 30
59 23 67 35 29 2 0 22
51 25 50 47 40 11 42 0
29 34 21 19 41 35 36 24
0 15 70 13 26 34 52 40
Result ref
0 50 44 17 15 37 35 40
77 0 49 21 62 27 56 44
57 24 0 28 26 48 36 11
68 36 29 0 55 30 59 23
67 35 29 2 0 22 51 25
50 47 40 11 42 0 29 34
21 19 41 35 36 24 0 15
70 13 26 34 52 40 62 0

Regards
Jonas