Activity
From 06/03/2014 to 07/02/2014
07/02/2014
- 06:47 PM Software Development: RE: uPP delay between transmissions
- We cannot get the uPP to work. For test we just use the FPGA to pass the uPP pins to FPGA output pin. The Enable pin ...
- 07:19 AM Software Development: RE: uPP delay between transmissions
- Ah, yes, I am sorry I forgot about the EMIFA scheduling delays. You are correct.
If you are using the reference P... - 12:55 AM Software Development: RE: uPP delay between transmissions
- We started with EMIFA. We got a delay of 11uSec between transfers as discussed in this post:
https://support.criti... - 11:49 AM Software Development: RE: Linker error on DSP application with Code Composer 6
- Thanks a lot to everybody.
It was a simple linker problem.
Silvano - Hello everybody.
We see an unexpected behaviour during simple debugging operations.
/*
* main.c
*/
#incl...
07/01/2014
- 04:30 PM Software Development: RE: Linker error on DSP application with Code Composer 6
- Note i found the generic c674x device under target: generic devices
!DSP_C674x.png! - 03:39 PM Software Development: RE: Linker error on DSP application with Code Composer 6
- Silvano,
Have you followed our guide to building a Hello World application?
https://support.criticallink.com/re... - Dear all,
we are trying to build a simple application on DSP using Code Composer 6 plus DSP/BIOS.
In the followi...
06/30/2014
- 04:18 PM Software Development: RE: uPP delay between transmissions
- Have you tried just writing to the FPGA via EMIFA? That would be a 16 2-byte word transfer. Even with 10 wait state...
- 03:11 PM Software Development: RE: uPP delay between transmissions
- Re-architecting our code is not really a vaiable solution. We have a feedback loop running in the DSP, that depends o...
06/28/2014
- 04:22 AM Software Development: RE: uPP delay between transmissions
- Hello,
First of all, using such small packet size you may not be able to completely eliminate the delay between s...
06/27/2014
- We are trying to use uPP to send data from the DSP to the FPGA. The problem is that there is a delay of about 8 micro...
06/26/2014
- 11:22 AM Software Development: RE: SSD on MityDSP-L138F
- Hannes,
As mentioned in the errata, they do not recommend the "reset" approach because they cannot guarantee that ... - 08:25 AM Software Development: RE: Where to download the document about Memory Map and Register Address of IO Board 80-000268RI-2C and OMAPL138F
- These are provided by TI. You can find them here: http://www.ti.com/product/OMAP-L138/technicaldocuments
You shoul... - 08:16 AM Software Development: RE: Where to download the document about Memory Map and Register Address of IO Board 80-000268RI-2C and OMAPL138F
- The memory map of the OMAP-L138 can be found on TI's main "OMAP-L138 web page":http://www.ti.com/product/omap-l138 (s...
06/25/2014
- only some brief documents are found in wiki,
Where can I download the document about Memory Map and Register Address... - 04:02 PM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Hello,Mike
Thank you very much.
- 12:42 PM FPGA Development: RE: DSP to FPGA SPI Setup Question
- What is your target update rate? Continuous?
You might try first to rip out all of the overhead on the tcDspFpgaS... - 11:32 AM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Hello,Mike
Thank you for your help.
I have attached two pic
----one is the SPI bits transfer rate(This is our des... - 10:47 AM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Can you check with a scope at what the clock rate is on the SPI device, and the interword write delay? I just want t...
- 10:39 AM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Update and followup question from the customer:
We have made the SPI work, but transmitting the word to word is sl... - 12:01 PM Software Development: RE: Interrupting the ARM from the DSP
- Thanks. This does what I wanted.
On the DSP side:... - 09:11 AM Software Development: RE: Interrupting the ARM from the DSP
- I think that you are confusing signals and interrupts a bit.
You need to write some kernel module code to register... - 08:26 AM Software Development: RE: Interrupting the ARM from the DSP
- Yes, I am familiar with DSPLink and am using it. However, I have time requirement that DSPLink cannot meet. Polling ...
- 08:01 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- There you are. Note that i had to change the initialization in the code as noted above.
- 07:26 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- If you don't mind, could you post your config.gz file?
- 05:37 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hey again,
i tried changing it from DMA to PIO. Now, everything seems to work. Device is readable, writable and mo... - Hey folks,
I'm trying to use a SSD instead of a HDD on the L138F.
I found in the errata that the OMAP-L138 has... - 02:12 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Jonathan, thank you, I will track your branch.
06/24/2014
- 05:41 PM Software Development: RE: Interrupting the ARM from the DSP
- Hello Mary,
I'm not sure what the problem is in your specific example as we almost always use DSPLink to to commu... - I would like to have the DSP (running BIOS 5) interrupt the ARM (running Linux MDK_2012-08-10)
In the DSP Code:
... - 12:04 PM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Andrey,
Not sure if its any help but I've pushed a work in progress 3.14 branch to our git. Its based off the main...
06/23/2014
- 10:25 AM PCB Development: RE: MityDSP-L138 processor running hot
- All unused connections are no connects.
- 09:59 AM PCB Development: RE: MityDSP-L138 processor running hot
- I have attached a plot showing the rise of the supply on the baseboard (channel 2) and the Mity card (channel 1). As ...
- 09:54 AM PCB Development: RE: MityDSP-L138 processor running hot
- What are you doing with unused connections on the module?
- 09:52 AM PCB Development: RE: MityDSP-L138 processor running hot
- It remains hot until the next power cycle. A reset cycle alone does not give an improvement.
- 09:15 AM PCB Development: RE: MityDSP-L138 processor running hot
- On non-FPGA variants, DVDD3318_A, DVDD3318_B, and DVDD3318_C are all tied to 3.3V.
Does the issue only occur durin... - 09:07 AM PCB Development: RE: MityDSP-L138 processor running hot
- All our I/O to the card is 3.3V. The OMAP processor has 3 configurable power groups which can be connected to 3.3V or...
- 07:56 AM PCB Development: RE: MityDSP-L138 processor running hot
- Ok.
I suspect the issue may be related to I/O voltage levels (you have I/Os being driven or pulled to a value larg... - 07:51 AM PCB Development: RE: MityDSP-L138 processor running hot
- We are using a baseboard developed for our application. I'm happy to share the schematic. Let me know how to get that...
- 07:06 AM PCB Development: RE: MityDSP-L138 processor running hot
- Hi Ed,
Are you running on a DevKit or on a custom board? Would you be willing to share your schematic (privately ... - We are some way into the development of using the MityDSP-L138 platform. I recently noticed that about 50% of the tim...
06/21/2014
- 03:49 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Jonathan, nothing special only setup kernel config (attached).
I use Yocto Project Daisy toolchain and kernel from g...
06/20/2014
- I am having some trouble with a data acquisition system.
Using MDK_2012-08-10
There are two tasks (among others... - 02:12 PM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Andrey, Can you share your linux 3.14 port. What did you have to change to get it working? Are you using device tr...
- Hello,ALL
I want to test the DspFpgaSpi, but not successfully setup,Could anyone give me some instructions?
Before ...
06/19/2014
- 09:13 PM FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello,
Your CORE_GPIO_MODULE and base address (0x66000080) do not match one another. The address should be the CO... - 02:26 PM FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the ... - 01:09 PM FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello,
... - 03:27 PM FPGA Development: RE: Help me check out the gpio Setup,It is not work.
- Thank you very much,Mike
- 03:11 PM FPGA Development: RE: Help me check out the gpio Setup,It is not work.
- The address for the constructor is not correct. The Address is: the CORE offset times 0x80 bytes + 0x66000000.
In... - Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the ... - 08:54 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Mike, thank you for fast response.
In Linux 3.14 (from Yocto Project) this leads to disabling cpufreq because it c... - 08:29 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- In the hardware, the TPS65023 used for the MityDSP-L138 has the following voltages that are defaulted using the hardw...
- Hello,
I use MityDSP-L138F and Linux kernel from git://support.criticallink.com/home/git/linux-davinci.git but wan...
06/18/2014
- 12:57 PM Software Development: RE: USB2.0 Host on MityDSP-L138F
- When I enabled the dma I got the following errors when i plugged in the flash drive....
- 11:07 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- I was able to scp a 12 MB file without any errors
- 11:05 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Also you can buy the cables prebuilt.
USB mini 5 pin to USB A Female
http://www.amazon.com/USB-Female-Mini-Male... - 10:41 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- How were you experiencing the unstable ethernet? Just transferring a file?
- 10:36 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- That changed stuff a bit. I now get more messages and the usb-msd driver seems to wake up.
But during initializati... - 10:12 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hannes, please let us know if this resolves your issue. We actually fixed this same problem on our MitySOM-335x modul...
- 09:54 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Got it working....
- 09:11 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- I don't think so. Udev primarily loads the driver and gets called once the driver does something. In the boot log you...
- 09:03 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Wondering if this is perhaps a udev issue?
- 08:58 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Exactly. But the mass storage driver itself gets loaded and then stalls (no /dev/sd* gets created).
- 08:23 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Ok I was able to get things to the point where it will atleast detect the insertion of the flash drive by changing th...
- 01:52 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- I tried changing between PIO and DMA before. That changed nothing about the problem - It enumerates the device and th...
06/17/2014
- Hello,All
I have followed the instruction posted by Michael Williamson. The spi core on FPGA
--https://support.cr... - 11:51 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Heres my bootlog. I'm having a hard time getting the mini usb working at all, in either host or peripheral mode. I ...
- 10:11 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- There you are.
That's the dmesg right after startup, with the card reader plugged in during startup. I enabled USB... - 09:40 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- OT: Hannes, can you please double check your email address in your profile, I (admin) am getting bounced email warnin...
- 09:27 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Could you post a full boot log? I'd like to compare it with what I'm getting. Also would be nice to see the connect...
- 04:16 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hi Bob,
Here's the file.
Thanks
Hannes
06/16/2014
- 10:08 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hannes,
Can you upload your kernel .config file? We have seen similar problems on our 335x product line that were ... - Hello everyone,
I'm trying to use the USB2-OTG on the MityDSP-L138F as a USB2 Host to connect a few USB-Mass Stora...
06/06/2014
- 06:36 PM Software Development: RE: DSP HelloWorld
- Flashing the 2014 MDK files solved all the problems. For some reason installing the U-boot bricked my board, but foll...
- 08:37 AM Software Development: RE: DSP HelloWorld
- The filesystem and kernel that ship preprogrammed on the L138 is quite old. You should have more luck if you flash t...
- 10:02 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Silvano, as a test, you can rename the securetty file which should eliminate any restrictions on root logins.
- 09:51 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- My securetty file has following at the top of the file which i didn't see in the file you posted....
- 09:49 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- I updated to the latest filesystem and got similar results to my previous post.
- 08:54 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Testing this on a L138 at my desk. I am able to login as root over ssh using any password including an empty passwor...
- 08:47 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Is there something wrong?
Any idea? - 08:19 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Attached you can find:
- a startup screenshot;
- the content of /etc/ folder;
- the file securetty.
Let me know... - 08:01 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- From serial I do the access without password but when I write "root" at login it tells me "login incorrect".
From et... - 08:00 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Normally, this is not a problem. can you check if there is an /etc/securetty file ( http://www.faqs.org/docs/securing...
- 07:58 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Did you set a password for the root shell? Normally there is no password by default. How did you set the password?
... - 07:57 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Does anybady has any suggestion?
It is important for me, not only to have the access from ethernet, but also from se...
06/05/2014
- I'm trying to setup a development environment for the MityDSP-L138 to write DSP code.
I got the DSP HelloWorld tes... - Dear all,
I have a strange problem.
I hava my MityDSP connected to my pc through both a serial cable and a ethe... - 06:24 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- I have corrected all the CRC error rounding the filesize parameters to the correct values.
I have also recompiled th...
06/04/2014
- 08:57 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- The filessize should be rounded to 0x800 bytes, which I think should be 0x150C800, not 0x150E000.
-Mike
- 08:49 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear all
As I got a lot of CRC errors, here are some question:
1 My .jffs2 file is about 21 MB (22070432 bytes) w...
06/03/2014
- 08:48 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Michael,
I tried to run the command you told me. Everything was ok until I copied the fpga_ctrl file on the t...
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