Activity
From 06/27/2014 to 07/26/2014
07/23/2014
- 11:06 PM FPGA Development: RE: fpgautil read Issue
- Hi Mike,
I found the issue. I was updating the edo_out signals only when rd was going high.
From the waveform... - 08:42 PM FPGA Development: RE: fpgautil read Issue
- Can you post (or email me) you VHDL source related to the loopback register?
Do you have Chipscope? It might be w... - I'm using MityDSP-L138 Board. I have implemented a Custom IP in the FPGA board.
I'm using the CS5 ARM Chipselect ...
07/22/2014
- 11:42 AM Software Development: RE: uPP receiving problem
- Hello Silvano,
No, the MDK uPP libraries are not setup to work with the debugger. In your code you can try settin... - 08:54 AM Software Development: RE: uPP receiving problem
- The strange behaviour still continue.
When we do not send data to uPP using the FPGA the program does not have the s... - 03:10 AM Software Development: RE: uPP receiving problem
- Thanks a lot for the suggestion.
I will check with my colleague the VHDL connection.
I also had a check at the opti...
07/21/2014
- 12:41 PM Software Development: RE: uPP receiving problem
- The strange stepping sounds exactly like when optimizations are turned on.
- 11:46 AM Software Development: RE: uPP receiving problem
- I'm not a VHDL guy, so I can't say whether this will work as you have it. It sounds like you and your VHDL guy shoul...
- 11:34 AM Software Development: RE: uPP receiving problem
- Here you can find the VHDL sources.
I cannot help you a lot with VHDL becuse it is developed by a colleague of mine.... - 11:19 AM Software Development: RE: uPP receiving problem
- Thanks a lot.
Now the working principles are clearer.
The problem now is that the software has a strange behaviour.... - 11:09 AM Software Development: RE: uPP receiving problem
- Each time you call receive, a DMA is set up to fill the buffer you pass. Once that DMA completes, no data will be tr...
- 10:08 AM Software Development: RE: uPP receiving problem
- Ok thank you.
I will try to change all the interrupt levels.
Another question is: but once the buffer is filled? Wh... - 10:05 AM Software Development: RE: uPP receiving problem
- I don't see any reason that it wouldn't work, but I have seen issues with some interrupt levels not working. I stron...
- 09:59 AM Software Development: RE: uPP receiving problem
- Thanks to have a look.
I have the signal enable and start always active.
I think that therefore is right to set bCh... - 09:49 AM Software Development: RE: uPP receiving problem
- A couple of things that I see are different from some code that I have working here:
I use nHWInterruptLevel = 7. ... - Dear all,
I am trying to use to uPP to receive data coming from the FPGA.
Attached you can find the code I wrot...
07/15/2014
- 04:39 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Jonathan,
Thank you for your patches, it's working for me!
I have applied and successfully rebuilt my kernel.
...
07/14/2014
- 11:39 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Ngoc,
Can you confirm that this is working for you and i'll move the changes into our main kernel branch?
I als... - 10:51 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- gpioToggle test passed when i just ran it. Not sure why....
- 10:24 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Reran some of the commands to see which fail. The ./PRU_memAccessL3andDDR can cause system segfaults as it appears t...
- 09:11 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Running through all the examples, atleast one of them seems to have caused a system segfault as not even reboot was a...
- 09:09 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Ngoc,
I have been working on getting this to work. So far i've integrated the patches which i've posted to a t... - 04:45 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
Thank you, I'm waiting for your patches. ^^
Regards,
Manh BT - 09:25 AM Software Development: RE: uBoot and USB using L138F SoM
- I have been looking into this. It seems that it was a mistake as the added resistor isn't mentioned in our Engineeri...
- 03:28 AM Software Development: RE: uBoot and USB using L138F SoM
- OK, the cable that I used was a miniAB to USB A plug which was then attached to a USB A to USB A gender changer (a li...
07/13/2014
- 10:18 PM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hello Manh BT,
The patches Mike described are in the mainline Linux kernel (http://kernel.org/). You can search fo... - 09:42 PM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Michael,
Thanks for your information, but where can I get above patches? Is it in Critical Link MDK ?
Regard...
07/11/2014
- 01:30 PM Software Development: RE: uBoot and USB using L138F SoM
- As per the On-The-Go spec, the mini USB adapter is supposed to tie the USB_ID pin to GND to indicate it should be put...
- 12:36 PM Software Development: RE: uBoot and USB using L138F SoM
- Yep, loading an image seems to be OK. Next week I'll try the whole image + rootfs and make sure that works too.
T... - 12:20 PM Software Development: RE: uBoot and USB using L138F SoM
- OK, now I get it. There's no resistor on my board pulling the ID pin down to 0V. I've just put a link between pins ...
- 12:07 PM Software Development: RE: uBoot and USB using L138F SoM
- The number is 80-000286RI-2
REV B
S/N 132556
Which bootloader are you using? I've been using my own compilation... - 12:05 PM Software Development: RE: uBoot and USB using L138F SoM
- Whats the part number of your dev kit? Should be a 80- number.
- 12:03 PM Software Development: RE: uBoot and USB using L138F SoM
- I just tested this by first plugging the flash drive into the full size usb port J102. With no luck. Then plugged d...
- 11:43 AM Software Development: RE: uBoot and USB using L138F SoM
- I forgot to say that I know that the USB port works because, once in Linux I can mount the drive OK and read/write fi...
- Hi there,
I'm using the L138F SoM on a REV B Industrial I/O board and I am trying to boot from a USB drive. uBoot i... - 08:31 AM Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
I think we need to add the following patches (from linus tree) to the kernel to instantiate the PRUSS drivers ... - Hi everyone!
I'm using MityDSP-L138F SOM + IO Industrial Board and now trying to work with PRU subsystem of OMAP-L...
07/03/2014
- 02:45 PM Software Development: RE: uPP delay between transmissions
- It was a cache invalidation issue. Calling BCACHE_wb() solved the problem.
I did find a small bug in the trasmit()... - 08:29 AM Software Development: RE: uPP delay between transmissions
- My first thought on seeing this is that it is probably a cache issue. After you set the values in the buffer, the va...
07/02/2014
- 06:47 PM Software Development: RE: uPP delay between transmissions
- We cannot get the uPP to work. For test we just use the FPGA to pass the uPP pins to FPGA output pin. The Enable pin ...
- 07:19 AM Software Development: RE: uPP delay between transmissions
- Ah, yes, I am sorry I forgot about the EMIFA scheduling delays. You are correct.
If you are using the reference P... - 12:55 AM Software Development: RE: uPP delay between transmissions
- We started with EMIFA. We got a delay of 11uSec between transfers as discussed in this post:
https://support.criti... - 11:49 AM Software Development: RE: Linker error on DSP application with Code Composer 6
- Thanks a lot to everybody.
It was a simple linker problem.
Silvano - Hello everybody.
We see an unexpected behaviour during simple debugging operations.
/*
* main.c
*/
#incl...
07/01/2014
- 04:30 PM Software Development: RE: Linker error on DSP application with Code Composer 6
- Note i found the generic c674x device under target: generic devices
!DSP_C674x.png! - 03:39 PM Software Development: RE: Linker error on DSP application with Code Composer 6
- Silvano,
Have you followed our guide to building a Hello World application?
https://support.criticallink.com/re... - Dear all,
we are trying to build a simple application on DSP using Code Composer 6 plus DSP/BIOS.
In the followi...
06/30/2014
- 04:18 PM Software Development: RE: uPP delay between transmissions
- Have you tried just writing to the FPGA via EMIFA? That would be a 16 2-byte word transfer. Even with 10 wait state...
- 03:11 PM Software Development: RE: uPP delay between transmissions
- Re-architecting our code is not really a vaiable solution. We have a feedback loop running in the DSP, that depends o...
06/28/2014
- 04:22 AM Software Development: RE: uPP delay between transmissions
- Hello,
First of all, using such small packet size you may not be able to completely eliminate the delay between s...
06/27/2014
- We are trying to use uPP to send data from the DSP to the FPGA. The problem is that there is a delay of about 8 micro...
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