Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

11/17/2014

05:16 PM Software Development: RE: FPGA configuration via u-Boot problem

You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o fil... Gregory Gluszek

07:29 AM FPGA Development: RE: PlanAhead issue

For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and high... Michael Williamson

03:21 AM FPGA Development: PlanAhead issue

Hi,
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Tem... Oleh Mela

11/14/2014

07:51 AM Software Development: RE: FPGA configuration via u-Boot problem

Hey,
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
By... Stefan Krassin

07:30 AM Software Development: FPGA configuration via u-Boot problem

Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from... Stefan Krassin

11/10/2014

01:52 PM Software Development: RE: Real time SATA writes

Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the ... Dominic Giambo

01:04 PM Software Development: RE: Real time SATA writes

After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally take... Mary Frantz

10/31/2014

10:44 AM FPGA Development: Clock for FPGA

Hi.
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
Thanks Oleh Mela

10/24/2014

10:41 AM PCB Development: RE: L138 SOM LEDs

Sorry,
On Non-FPGA modules:
D1 is connected to R16 (GP6_12) of the OMAP-L138.
D2 is connected to R17 (GP6_13... Michael Williamson

10:05 AM PCB Development: RE: L138 SOM LEDs

Hi Mike,
The SOM we are using is the non-FPGA version. What do D1 and D2 connect to?
Thanks,
Anton Anton Kitai

07:22 AM PCB Development: RE: L138 SOM LEDs

D1 is connected to the FPGA_DONE pin on the FPGA configuration block.
D2 is connected to P15 of the FPGA IO_L74P_A... Michael Williamson

10:03 AM PCB Development: RE: MityDSP-L138 Boot Problem

This issue has been resolved - we had left an uterminated SPI1_CLK signal trace on our base board at an unpopulated d... Anton Kitai