Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

03/12/2015

11:06 AM FPGA Development: RE: FPGA serial programming interface

We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail ... Alexander Block

03/11/2015

10:23 AM FPGA Development: RE: FPGA serial programming interface

Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use par... stephan berner

10:18 AM FPGA Development: RE: FPGA serial programming interface

I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required ... Alexander Block

08:32 AM FPGA Development: RE: FPGA serial programming interface

SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing... Alexander Block

03/10/2015

05:04 PM FPGA Development: RE: FPGA serial programming interface

I understand that. However, I would like to configure the FPGA in serial slave mode. stephan berner

05:01 PM FPGA Development: RE: FPGA serial programming interface

SB,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 pr... Alexander Block

03:36 PM FPGA Development: FPGA serial programming interface

hi,
are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the... stephan berner

03/05/2015

05:20 PM Software Development: RE: Write to SharedMem from DSP and read it from ARM

Thanks for the cache info. Completely missed that part.
I reverted to the original code, and I've added BCACHE_wb(... Frank C