Activity
From 05/22/2024 to 06/20/2024
06/20/2024
- 07:57 PM Software Development: RE: RS485 Direction Control on UART1
- How long are you looking for?
The kernel documentation mentions getting extended distance for rs232 by using UTP c... - 03:43 PM Software Development: RE: RS485 Direction Control on UART1
- Hi Jonathan,
thanks for the quick response. I will look into the 8250 driver, it might be useful (if only for my ...
06/19/2024
- 07:09 PM Software Development: RE: RS485 Direction Control on UART1
- The serial 8250 driver has an rs485 mode which we extended to allow using a gpio to generate a RS485 TX enable. Howe...
- Hi all,
My application requires installation embedded in a battery power system with long wire. I would like acces...
06/10/2024
- 11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read reque... - 07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk...
06/05/2024
- 09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r... - 12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown bel...
06/03/2024
- 03:08 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If t...
- hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading ...
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