Activity

From 05/27/2024 to 06/25/2024

09:59 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early: The kernel driver code for RS485 support can be found here: https://support.criticallink.com/gitweb/?p=linux-davinci.... Jonathan Cormier
06:58 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early: Seems a "paste" didn't work as expected...
SER_RS485_USE_GPIO is the same as 1<<5 Fred Weiser
06:54 PM Software Development: Serial port 2 issue, RS485, RTS drops to early: We are having a problem with serial port ttyS2 on our L138 SoM which I believe resides in the Linux driver or the TI ... Fred Weiser

07:57 PM Software Development: RE: RS485 Direction Control on UART1: How long are you looking for?
The kernel documentation mentions getting extended distance for rs232 by using UTP c... Jonathan Cormier
03:43 PM Software Development: RE: RS485 Direction Control on UART1: Hi Jonathan,
thanks for the quick response. I will look into the 8250 driver, it might be useful (if only for my ... Michael Bisbano

07:09 PM Software Development: RE: RS485 Direction Control on UART1: The serial 8250 driver has an rs485 mode which we extended to allow using a gpio to generate a RS485 TX enable. Howe... Jonathan Cormier
04:36 PM Software Development: RS485 Direction Control on UART1: Hi all,
My application requires installation embedded in a battery power system with long wire. I would like acces... Michael Bisbano

11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem: There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read reque... Michael Williamson
07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem: Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk... Kyungguk Bok

09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem: Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r... Gregory Gluszek
12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem: Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown bel... Kyungguk Bok

03:08 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem: The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If t... Jonathan Cormier
08:57 AM Software Development: FPGA (FIFO) -> DSP (DMA) transfer problem: hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading ... Kyungguk Bok

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Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)