Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

06/27/2024

09:06 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Changing the timer is probably not in my best interest; my project supports down to 1200 baud with packets up to 256 ... Fred Weiser

06:12 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Here's the snip:... Fred Weiser

05:45 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Looks like wait_for_xmitr has a 10ms timeout, this might explain why the TXEN is enabled for a constant time. At low... Jonathan Cormier

04:19 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

What does your pinmux look like for UART2? Jonathan Cormier

03:36 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Please see two attached scope traces; the second with a 7 character buffer, the first with a 16 character buffer. I w... Fred Weiser

02:31 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

It looks like (in the 3.2 kernel anyway) the only serial port driver that supports the delay_rts_after_send option is... Tim Iskander

01:46 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Thanks for the ideas; I'm looking into the code cited above now; I don't have any new news there at this time.
Ho... Fred Weiser

01:05 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

My suspicion is that the register read in wait_for_xmitr() is "lying" and the UART is actually still serializing the ... Tim Iskander

08:47 PM Software Development: RE: RS485 Direction Control on UART1

Seems like it could work. Good find. Jonathan Cormier

07:17 PM Software Development: RE: RS485 Direction Control on UART1

I did come across this application note from TI: https://www.ti.com/lit/ug/tidubw6/tidubw6.pdf?ts=1719509747706
(if ... Michael Bisbano

06/25/2024

09:59 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

The kernel driver code for RS485 support can be found here: https://support.criticallink.com/gitweb/?p=linux-davinci.... Jonathan Cormier

06:58 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Seems a "paste" didn't work as expected...
SER_RS485_USE_GPIO is the same as 1<<5 Fred Weiser

06:54 PM Software Development: Serial port 2 issue, RS485, RTS drops to early

We are having a problem with serial port ttyS2 on our L138 SoM which I believe resides in the Linux driver or the TI ... Fred Weiser

06/20/2024

07:57 PM Software Development: RE: RS485 Direction Control on UART1

How long are you looking for?
The kernel documentation mentions getting extended distance for rs232 by using UTP c... Jonathan Cormier

03:43 PM Software Development: RE: RS485 Direction Control on UART1

Hi Jonathan,
thanks for the quick response. I will look into the 8250 driver, it might be useful (if only for my ... Michael Bisbano

06/19/2024

07:09 PM Software Development: RE: RS485 Direction Control on UART1

The serial 8250 driver has an rs485 mode which we extended to allow using a gpio to generate a RS485 TX enable. Howe... Jonathan Cormier

04:36 PM Software Development: RS485 Direction Control on UART1

Hi all,
My application requires installation embedded in a battery power system with long wire. I would like acces... Michael Bisbano

06/10/2024

11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read reque... Michael Williamson

07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk... Kyungguk Bok

06/05/2024

09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r... Gregory Gluszek

12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown bel... Kyungguk Bok

06/03/2024

03:08 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If t... Jonathan Cormier

08:57 AM Software Development: FPGA (FIFO) -> DSP (DMA) transfer problem

hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading ... Kyungguk Bok