Activity
From 01/21/2013 to 02/19/2013
02/04/2013
- 08:12 AM FPGA Development: RE: About CE4 CE5 and INT6's pin asisgnment in FPGA
- Hello.
CE4 is connected to W15 of the FPGA (Bank 4).
CE5 is connected to AA15 of the FPGA (Bank 4).
GP [6] is co... - Hi，
I want to design a sync fifo in the FPGA, which will use a synchronous interface in EMIF. So it is better
t...
Also available in: Atom
Go to top
