Activity
From 10/20/2013 to 11/18/2013
11/18/2013
- 05:04 PM FPGA Development: RE: Unable to access Linux
- Hi Jack,
We haven't trying using an Altera MMK, we instead us the USB Blaster or the USB Blaster II directly. Is ... - Hi,
I am having trouble accessing the Linux system on the SD card, when the MityARM is connected to the PC, meanin... - 05:01 PM FPGA Development: RE: Input/Output interfacing
- Hi Rich,
You need to be careful with the pin assignments. If you change an assignment that is by default controll... - 04:57 PM FPGA Development: RE: FPGA - HPS DDR Memory
- Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon mem... - Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my comp...
11/14/2013
- 02:39 PM FPGA Development: RE: Input/Output interfacing
- Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to ...
11/13/2013
- 01:41 PM FPGA Development: RE: Input/Output interfacing
- The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/image...
11/12/2013
- 07:03 PM FPGA Development: RE: Input/Output interfacing
- Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connect...
- 07:01 PM FPGA Development: RE: Input/Output interfacing
- Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a l... - 05:49 PM FPGA Development: RE: Input/Output interfacing
- Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported ... - I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so t...
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