Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/19/2013

05:49 PM FPGA Development: Ethernet

Hi,
How can I configure the FPGA such that the ethernet will still be functioning after I program it. I notice tha... Anonymous

05:25 PM FPGA Development: RE: Clock

There is a 25 Mhz clock brought in on the main HPS_CLK1 input (pin E20). It's actually defined in the Qsys HPS compo... Michael Williamson

05:18 PM FPGA Development: Clock

Hi,
Where is the clock on the MityArm?
I am using your mityarm_5csx_dev_board project, and it's not there. Coul... Anonymous

11/18/2013

05:04 PM FPGA Development: RE: Unable to access Linux

Hi Jack,
We haven't trying using an Altera MMK, we instead us the USB Blaster or the USB Blaster II directly. Is ... Michael Williamson

04:38 PM FPGA Development: Unable to access Linux

Hi,
I am having trouble accessing the Linux system on the SD card, when the MityARM is connected to the PC, meanin... Anonymous

05:01 PM FPGA Development: RE: Input/Output interfacing

Hi Rich,
You need to be careful with the pin assignments. If you change an assignment that is by default controll... Michael Williamson

04:57 PM FPGA Development: RE: FPGA - HPS DDR Memory

Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon mem... Michael Williamson

04:42 PM FPGA Development: FPGA - HPS DDR Memory

Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my comp... Anonymous

11/14/2013

02:39 PM FPGA Development: RE: Input/Output interfacing

Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to ... Rich Bagdazian

11/13/2013

01:41 PM FPGA Development: RE: Input/Output interfacing

The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/image... Michael Williamson

11/12/2013

07:03 PM FPGA Development: RE: Input/Output interfacing

Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connect... Rich Bagdazian

07:01 PM FPGA Development: RE: Input/Output interfacing

Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a l... Rich Bagdazian

05:49 PM FPGA Development: RE: Input/Output interfacing

Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported ... Daniel Vincelette

04:47 PM FPGA Development: Input/Output interfacing

I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so t... Rich Bagdazian