Activity
From 10/03/2014 to 11/01/2014
10/29/2014
- CK 10:58 AM Software Development: RE: Performance problem with baremetal code
- In the meanwhile and after an ARM Cortex training I've found the root cause of the problem:
For enabling the caches, you have also to initialize the MMU, e.g. with the attached version of performance.c. Nevertheless the baremetal code...
10/20/2014
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04:34 PM
FPGA Development: RE: Modular SGDMA
- Hi Dan,
I polling the FIFO empty signal for the both the dispatcher and write master to ensure that only when both FIFOs are empty when I will continue.
The delay varies, it's hard to predict.
Ideally we don't want to put any sl...
10/17/2014
- DV 04:53 PM FPGA Development: RE: Modular SGDMA
- Hi Jack,
You could try polling the dispatcher's busy bit instead but I'm not quite sure if that would solve your issue. Any idea at how long the delay is for? Does the FIFO overflow because of it? Also you might want to put a bit of a... -
03:57 PM
FPGA Development: Modular SGDMA
- Hi
I'm running into a difficulty with the Modular SGDMA that is used in the HPS Memory example.
I have to send dispatchers repeatedly in a infinite loop. I have it designed such that after I send the command to write the dispatcher...