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From 11/23/2014 to 12/22/2014

12/11/2014

07:50 PM FPGA Development: 100MHz Input clock (CLK2 - DDR3) Issue
A customer has the 100MHz DDR3 clock being fed into the module through Pins 117 and 119 on a custom carrier board and... Alexander Block

11/25/2014

07:46 AM FPGA Development: RE: Writing to HPS memory
I would recommend contacting your Arrow FAE or Altera for help with the device tree generation / sopcinfo file.
Yo...
Michael Williamson
07:39 AM FPGA Development: Writing to HPS memory
Hi,
I'm want to use the hps_ddr_write_example design from critical link and test it on Arrow Terasic Cyclone V SOC...
Vidya Govindan
 

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