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From 12/01/2014 to 12/30/2014

12/11/2014

AB 07:50 PM FPGA Development: 100MHz Input clock (CLK2 - DDR3) Issue
A customer has the 100MHz DDR3 clock being fed into the module through Pins 117 and 119 on a custom carrier board and is using it to clock some ADC data. However after a little run-time it stops working as noted below: Alexander Block
 

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