Activity
From 04/30/2015 to 05/29/2015
05/29/2015
- AL 07:27 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi Mike,
Thanks for all the support. I've managed to solve the problem by downloading the 5CSX Project once again, downloading a new U-Boot version and adding the board specific files to U-Boot and compiling everything again. I still ... - MW 06:53 AM Software Development: RE: PHY not working with QSPI flash boot
- I am checking with our hardware guy here but I don't think the MPU rate is altered by the BOOTSEL pins after u-Boot.
I think the MPU rate is configured in the QSYS HPS configuration setup and the PLL settings are passed via headers to... - FR 03:31 AM FPGA Development: RE: HSMC1 pinout
- Alex,
thank you for clearing that up!
B) Just for the record, SMC1_SMSDA should be SoM pin 54 and HSMC1_SMSCL should be SoM pin 52.
C) Yes, the usage of those pins is quasi-static, they form part of a 9 bit configuration interfa...
05/28/2015
- AL 11:32 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi Mike,
I have tested it with the image that is available here: http://support.criticallink.com/files/mitysom-5csx/sd_image_MitySOM-5CSX_rev3A.zip.
The Ethernet link appears to be 100Mbps as well.
I hadn't notice the different c... - MW 10:19 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi,
We are not aware of any problem until your post. We had tried to reproduces this problem after you originally posted and didn't see the issue. Sorry I did not mention it. I have asked the engineer to re-run it and capture the re... - AL 10:01 AM Software Development: RE: PHY not working with QSPI flash boot
- I just want to report that this problem is _not_ present when using an Altera Cyclone V DevKit.
I have no problem with the PHY when booting from QSPI flash and I am able to obtain an IP address via DHCP and load a Linux Kernel via TFTP... - AL 09:00 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi Mike,
Thanks for replying. The U-Boot environments are identical. The driver should also be there as I have just noticed, after several attempts, that someties U-Boot does manage to find the interface (although it doesn't work prop... - MW 07:28 AM Software Development: RE: PHY not working with QSPI flash boot
- Sorry,
The only thing that comes to mind is if somehow the uBoot environment has changed or the SPL build removed the phylib or emac driver. You might compare the printenv's from both configurations a little closer. You might also m... - AL 06:08 AM Software Development: RE: PHY not working with QSPI flash boot
- Any ideas of what the problem might be?
Can somebody at least reproduce this behavior?
- AB 11:08 AM FPGA Development: RE: HSMC1 pinout
- Floria,
A) We confirmed that the .tcl script is in fact incorrect for that pin-assignment.
Correct pin assignment (as you noted): - AL 04:30 AM Software Development: RE: PCI-e Intel - System crash
- It's a total freeze, no dumps are written. Guess the only option is to use the DS-5 Kernel/Device Drivers debug capabilities.
Any other ideas?
Thanks,
Alex
05/27/2015
- AL 09:38 AM Software Development: RE: PCI-e Intel - System crash
- I don't seem to get any oops or panic, it just hangs. I'm attaching the output of dmesg up to the point where the system crashes
(this is for Critical Link's image, i.e. 3.12.0). To get a proper dump I'll need to re-compile the kernel ... - MW 08:36 AM Software Development: RE: PCI-e Intel - System crash
- Can you dump out the kernel messages (oops? panic? dmesg?)?
-Mike
- Hello,
I am trying to get the PCI-e interface on the MitySoM DevKit (RC-3C version) to work with an Intel 82574L Gigabit Network card
(the same that is used at the RocketBoards example).
I have tried to use both the pre-compiled im...
05/26/2015
- Hi,
I am using the "mityarm_5csx_dev_board_hsmc_setup.tcl":https://support.criticallink.com/redmine/boards/47/topics/3348?r=3352#message-3352 to define the pinout of the HSMC1 interface of my FPGA design, and found a discrepancy in th...
05/20/2015
- Hi,
I am trying to set up the MitySOM such that U-Boot is stored on the flash memory and the Linux Kernel, DTS and FPGA image are loaded via TFTP.
Whenever I boot from the SD card with a preloader and U-boot compiled according to the...
05/19/2015
- AL 03:30 AM Software Development: RE: Boot configuration jumpers
- Thank you very much. As I've seen the labeling is to the right of the switch (in my case), hence I didn't pay attention to it. Also, what I wrote should obviously read 101 = 0x5: 3.3 V SD/MMC, lack of sleep does that.
Best,
Alexandre
05/18/2015
- AD 11:30 AM Software Development: RE: Boot configuration jumpers
- Sorry this isn't clear. There is silkscreen labeling below the switch corresponding to the switch locations 1-10: MSEL[0-4], CSEL[0-1], BSEL[0-2]. CSEL is Clock Select and BSEL is Boot Select. The QSPI interface is running at 1.8V and...
- Hi,
Can someone please shed me some light on the boot configuration jumpers of the MitySOM-5CSX Dev-Kit? On the datasheet it simply says:
_"The MitySOM-5CSX Development Kits default boot configuration mode is shown in Figure 3 below....
04/30/2015
- MW 07:53 AM Software Development: RE: Bare-metal interrupt handling working only in debugger
- Hi Alex,
Glad you solved your issue, sorry we didn't provide much help. We don't have a lot of folks trying to do Bare-Metal (and we don't do it often either).
-Mike - AL 06:22 AM Software Development: RE: Bare-metal interrupt handling working only in debugger
- No, that was obviously not the reason. The unhosted and hosted linker scripts do link against different libraries but that only seems matters for stdio. I was able to solve the problem by rewritting everything from scratch. The way I was...