Activity
From 05/23/2015 to 06/21/2015
06/03/2015
- AL 09:15 AM Software Development: RE: PCI-e Intel - System crash
- Hi Mike,
I'm using the pre-compiled reference image from your PCI Hard IP page. I didn't try to compile the project myself (although I suppose the result will be the same if I do so).
Thanks for all the support.
Alex - MW 08:44 AM Software Development: RE: PCI-e Intel - System crash
- Hi Alex,
Sorry about this. My guess is that the FPGA project we provided is either not routing the PCIe interrupt to the same spot in the HPS that the device tree is configured for or perhaps not at all. The QSYS project would show ... - AL 04:45 AM Software Development: RE: PCI-e Intel - System crash
- Okay, a couple more informations:
The 3.12 image provided by Critical Link on the PCI Hard IP page seems to have been compiled without CONFIG_PCI_MSI=y, since when I try to load the intel driver with MSI interrupts compiled in I get
06/02/2015
- AL 12:43 PM Software Development: RE: PCI-e Intel - System crash
- Comparing both outputs of lspci, it seems that in the MitySoM case, MSIs are disabled:
- AL 12:36 PM Software Development: RE: PCI-e Intel - System crash
- Hi Mike,
So I have tested both cards on a x86 PC with Kernel 3.12 and 3.18.9 and everything works as it should (using the same drivers, i.e. E1000E and XHCI).
I have also downloaded the pre-compiled image (PCIe Root Port with MSI) ...
06/01/2015
- AL 10:34 AM Software Development: RE: PCI-e Intel - System crash
- Hi Mike,
Thanks for your support.
The boot pci-e related messages are (using Critical Link's images): - MW 09:57 AM Software Development: RE: PCI-e Intel - System crash
- Yeah,
I am wondering if this error message might be an issue: - MW 09:53 AM Software Development: RE: PCI-e Intel - System crash
- Hi Alex,
On the DevKit, we have found that the PCIe card edge is a little shakey without a mechanical mount (e.g., if the card tips forward and backward the PCIe signalling doesn't work well).
Are you running the same Linux version... - AL 09:15 AM Software Development: RE: PCI-e Intel - System crash
- I have tested a NEC chipset based USB 3.0 PCI-e controller card and I also can't manage to get everything to work.
Again I have tested the official 3.12 image from Critical Link (plus official DTB and FPGA image) and have tested with my...
05/29/2015
- AL 07:27 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi Mike,
Thanks for all the support. I've managed to solve the problem by downloading the 5CSX Project once again, downloading a new U-Boot version and adding the board specific files to U-Boot and compiling everything again. I still ... - MW 06:53 AM Software Development: RE: PHY not working with QSPI flash boot
- I am checking with our hardware guy here but I don't think the MPU rate is altered by the BOOTSEL pins after u-Boot.
I think the MPU rate is configured in the QSYS HPS configuration setup and the PLL settings are passed via headers to... - FR 03:31 AM FPGA Development: RE: HSMC1 pinout
- Alex,
thank you for clearing that up!
B) Just for the record, SMC1_SMSDA should be SoM pin 54 and HSMC1_SMSCL should be SoM pin 52.
C) Yes, the usage of those pins is quasi-static, they form part of a 9 bit configuration interfa...
05/28/2015
- AL 11:32 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi Mike,
I have tested it with the image that is available here: http://support.criticallink.com/files/mitysom-5csx/sd_image_MitySOM-5CSX_rev3A.zip.
The Ethernet link appears to be 100Mbps as well.
I hadn't notice the different c... - MW 10:19 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi,
We are not aware of any problem until your post. We had tried to reproduces this problem after you originally posted and didn't see the issue. Sorry I did not mention it. I have asked the engineer to re-run it and capture the re... - AL 10:01 AM Software Development: RE: PHY not working with QSPI flash boot
- I just want to report that this problem is _not_ present when using an Altera Cyclone V DevKit.
I have no problem with the PHY when booting from QSPI flash and I am able to obtain an IP address via DHCP and load a Linux Kernel via TFTP... - AL 09:00 AM Software Development: RE: PHY not working with QSPI flash boot
- Hi Mike,
Thanks for replying. The U-Boot environments are identical. The driver should also be there as I have just noticed, after several attempts, that someties U-Boot does manage to find the interface (although it doesn't work prop... - MW 07:28 AM Software Development: RE: PHY not working with QSPI flash boot
- Sorry,
The only thing that comes to mind is if somehow the uBoot environment has changed or the SPL build removed the phylib or emac driver. You might compare the printenv's from both configurations a little closer. You might also m... - AL 06:08 AM Software Development: RE: PHY not working with QSPI flash boot
- Any ideas of what the problem might be?
Can somebody at least reproduce this behavior?
- AB 11:08 AM FPGA Development: RE: HSMC1 pinout
- Floria,
A) We confirmed that the .tcl script is in fact incorrect for that pin-assignment.
Correct pin assignment (as you noted): - AL 04:30 AM Software Development: RE: PCI-e Intel - System crash
- It's a total freeze, no dumps are written. Guess the only option is to use the DS-5 Kernel/Device Drivers debug capabilities.
Any other ideas?
Thanks,
Alex
05/27/2015
- AL 09:38 AM Software Development: RE: PCI-e Intel - System crash
- I don't seem to get any oops or panic, it just hangs. I'm attaching the output of dmesg up to the point where the system crashes
(this is for Critical Link's image, i.e. 3.12.0). To get a proper dump I'll need to re-compile the kernel ... - MW 08:36 AM Software Development: RE: PCI-e Intel - System crash
- Can you dump out the kernel messages (oops? panic? dmesg?)?
-Mike
- Hello,
I am trying to get the PCI-e interface on the MitySoM DevKit (RC-3C version) to work with an Intel 82574L Gigabit Network card
(the same that is used at the RocketBoards example).
I have tried to use both the pre-compiled im...
05/26/2015
- Hi,
I am using the "mityarm_5csx_dev_board_hsmc_setup.tcl":https://support.criticallink.com/redmine/boards/47/topics/3348?r=3352#message-3352 to define the pinout of the HSMC1 interface of my FPGA design, and found a discrepancy in th...