Activity
From 01/11/2016 to 02/09/2016
02/09/2016
- DV 05:16 PM Software Development: RE: Board info files MittySOM-5cse-l2-3y8
- Hi Brian,
It appears that all these issues are stemming from the SOM not being able to mount /proc. Can you make sure that CONFIG_PROC_FS is enabled in your defconfig? Also would you mind doing a quick diff of the .config and mitysom5... - BW 08:34 AM Software Development: RE: Board info files MittySOM-5cse-l2-3y8
- Hello Dan,
Thanks for the timely reply. Yes, I was using the Altera Sopc2dts tool to generate the DTB. I have rebuilt the project based on the .dts that you specified above. I was able to get past the Loading Kernel.
I have anothe...
02/04/2016
- DV 03:59 PM Software Development: RE: Board info files MittySOM-5cse-l2-3y8
- Hello Brian,
Are you trying to manually by hand create the DTS or are you using the Altera Sopc2dts tool that will take the output of your quartus build and create the DTS for you?
We normally go about creating the DTS by hand. The... - I'm having trouble creating a dts file that shows the peripherals on the fpga of my design. I can't find the correct xml board info files needed to create the dts file. Any help would be appreciated. The goal is to create all the necessa...
01/15/2016
- AD 02:57 PM FPGA Development: RE: LVDS transceiver for 1000Mb Ethernet MAC & 1000Base-X problem
- Hi Charles,
The GXB TX details can be found in Altera's documentation:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5v3.pdf
Are you using the on-chip biasing network and termination, o...
01/12/2016
- Hi,
I have been attempting to use the development kit to setup and implement a system which interfaces to an externally connected SFP module which I have connected via the SPIe connection to the dev board. I instantiated the TSE Ethern...