Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

06/20/2017

05:59 PM FPGA Development: RE: Power fail interrup

Clyde,
Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as... Alexander Block

05:14 PM FPGA Development: RE: Power fail interrupt

What more is there to say, really? We have a low voltage supervisor in our design and when the power is going to fai... Clyde Shappee

04:45 PM FPGA Development: RE: Power fail interrup

Hello Clyde,
Could you describe the situation a bit more?
Thanks!
Dan Daniel Vincelette

02:05 PM FPGA Development: Power fail interrup

What is the recommended input to the SOM for a power fail interrupt?
clyde Clyde Shappee

06/14/2017

09:10 PM PCB Development: VCCPGM and VCCBAT

Hello, I have a 5CSX-H6-4YA-RI board.
What do I pull the MSEL lines up to when I pull them up.
(what is VCCPGM p... Craig Drennan

06/07/2017

02:20 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

Hello Mike and Adam,
I very much appreciate you both providing other suggestions readily available with our MitySO... Jared Kirschner

06/02/2017

12:14 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

The QSPI NOR is supported by the MTD layer, so you should be able to partition it and mount it using JFFS2 (or perhap... Michael Williamson

12:05 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

We're using the 5CSX-H6-4YA so we should have 32MB of QSPI NOR, and we are booting from SD card, though it's possible... Stephen Snyder

10:25 AM Software Development: RE: Using EEPROM available on MitySOM-5CSX

Hi Jared,
If you are looking for a small amount of space, there is also some memory available in the RTC. There i... Adam Dziedzic

06/01/2017

11:52 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

Hi Jared,
Before you get into the I2C EEPROM, does the MitySOM you are using have the QSPI NOR FLASH installed (mo... Michael Williamson

10:39 PM Software Development: Using EEPROM available on MitySOM-5CSX

+Context:+
My team would like to store some non-volatile data specific to a unit of hardware (independent of the S... Jared Kirschner

05/23/2017

08:32 PM Software Development: RE: Altera spi

Brian,
Glad to hear it! You're welcome
Dan Daniel Vincelette

06:24 PM Software Development: RE: Altera spi

Dan,
Got it working. Thanks for all the help.
Brian Brian Wentworth

06:12 PM Software Development: RE: Altera spi

Brian,
It looks like the Altera GPIO documentation is wrong, in the the driver it's looking for GPIO interrupts to... Daniel Vincelette

05:57 PM Software Development: RE: Altera spi

Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian Brian Wentworth

05:55 PM Software Development: RE: Altera spi

Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian Brian Wentworth

05:28 PM Software Development: RE: Altera spi

Brian,
I think this variable was changed to "altr,interrupt-trigger" in the newer kernel. Here is the documentatio... Daniel Vincelette

05:23 PM Software Development: RE: Altera spi

Dan,
I have most of it working. The only problem I see now is the gpio not showing up. I'm getting the following err... Brian Wentworth

02:38 PM Software Development: RE: Altera spi

Brian,
Can you post your boot output?
I would recommend doing a diff of the DE0 nano board dts and that one. Th... Daniel Vincelette

08:21 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Glad to hear you got it to work!
Dan Daniel Vincelette

06:48 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Dan,
solved also this step!
I rebuilt the my kernel version using the default .config you suggested me, modified... Gianni Casonato

05:20 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Glad to hear!
I used our mitysom5csx_devkit_defconfig that is part of our 3.16 kernel
kernel: https://support.c... Daniel Vincelette

05:04 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Dan,
thanks for it.
I've added the spi0 section at the bottom of my dts and it works!!! Fantastic!!
The only po... Gianni Casonato

02:32 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Hello Gianni,
I see that you've tried to add both the spidev devices to a FPGA spi core and the HPS peripheral. I ... Daniel Vincelette