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From 06/29/2019 to 07/28/2019
07/03/2019
- 11:04 AM FPGA Development: RE: Set timing constraints
- Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the... - Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I...
07/01/2019
- 11:03 AM Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9
- Hi Wesley
Thank you for the proposed code change, that did the trick!
I think @static DRIVER_ATTR(fpga_uinput, S_IR...
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