Project

General

Profile

Activity

From 07/03/2019 to 08/01/2019

07/03/2019

11:04 AM FPGA Development: RE: Set timing constraints
Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the... Michael Williamson
09:20 AM FPGA Development: Set timing constraints
Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I... Davide Vaccaro
 

Also available in: Atom

Go to top
Add picture from clipboard (Maximum size: 1 GB)