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From 07/04/2024 to 08/02/2024

08/01/2024

12:52 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And no...
Bhardwaj Kotha

07/31/2024

03:39 PM Software Development: RE: Receive and send data using vlan tag
Bhardwaj
There should be no devicetree changes necessary to use the VLAN feature of the Ethernet.
You verified that...
Tim Iskander
05:55 AM Software Development: Receive and send data using vlan tag
Hi,
I am working on ethernet using vlan. I had used the ip command to create the vlan after that some data sent f...
Bhardwaj Kotha

07/25/2024

07:47 PM Software Development: RE: how to access gpio using pio ip core in c code
Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is reques...
Gregory Gluszek

07/24/2024

07:11 AM Software Development: RE: how to access gpio using pio ip core in c code
Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using...
Bhardwaj Kotha

07/23/2024

04:12 PM Software Development: RE: how to access gpio using pio ip core in c code
It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp... Gregory Gluszek

07/22/2024

03:16 PM Software Development: RE: how to access gpio using pio ip core in c code
Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform des...
Bhardwaj Kotha

07/19/2024

02:11 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if y...
Daniel Vincelette
06:45 AM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before u...
Bhardwaj Kotha

07/16/2024

07:40 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The m...
Daniel Vincelette

07/15/2024

06:58 PM Software Development: RE: how to access gpio using pio ip core in c code
The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory... Gregory Gluszek

07/13/2024

03:16 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hi,
with the provided reference project there is no packet loss but there are timing errors (screenshots attached)...
Bhardwaj Kotha

07/11/2024

01:39 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Al... Daniel Vincelette
12:05 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit sig... Bhardwaj Kotha

07/10/2024

01:08 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hello,
For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that wa...
Daniel Vincelette
12:07 PM Software Development: RE: how to access gpio using pio ip core in c code
Yes, I wanted to send the 256 BITS of raw data from HPS to FPGA. Can you give me the supplies for that. Bhardwaj Kotha

07/08/2024

03:09 PM Software Development: RE: Get URL from jenkins file
I just did a clean pull of the kernel and built it using the poky 3.0.4 sdk with no issues.
It sounds like either th...
Tim Iskander
01:20 PM Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS
This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the o... Gregory Gluszek
01:18 PM Software Development: RE: how to access gpio using pio ip core in c code
Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what erro...
Gregory Gluszek

07/07/2024

01:01 PM Software Development: RE: Get URL from jenkins file
Hi,
I have downloaded the kernel from https://git.criticallink.com/gitweb/?p=linux-socfpga.git;a=shortlog;h=refs...
Bhardwaj Kotha

07/05/2024

08:53 AM Software Development: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS
Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block wi...
Bhardwaj Kotha
08:51 AM Software Development: how to access gpio using pio ip core in c code
Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block...
Bhardwaj Kotha

07/04/2024

07:34 AM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM
Hi Daniel,
Now am able to generate the boot files.
Thanks & Regards,
Bhardwaj
Bhardwaj Kotha
07:02 AM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hi,
I donot have much resources, as my application need more resources, I wanted to use HPS EMAC. And I am not going...
Bhardwaj Kotha
 

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