Activity

From 11/17/2025 to 12/16/2025

DV 02:54 PM FPGA Development: RE: Ethernet PHY configuration and SSH access: Hi Atef,
You should be able to do this via ethtool: Daniel Vincelette
AF 02:50 PM FPGA Development: RE: Ethernet PHY configuration and SSH access: Hi Zach,
Could you please generate a Linux image for the 5CSX-H6-4YA based on the Linux image available at the following link (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki), but configured so that the Ethernet li... Anonymous fpga
MW 10:25 AM FPGA Development: RE: Ethernet PHY configuration and SSH access: Hello,
For layout, the two groups you have outlined in your schematic snippet should be matched in length and ideally be on the same layer. The clocks should be separated from the data lanes by at least 5x trace width. We usually ... Michael Williamson
AF 08:47 AM FPGA Development: RE: Ethernet PHY configuration and SSH access: Hi Zach,
Just a quick update on my side.
I am now able to communicate over Ethernet with our custom carrier board. However, in some cases I still observe data loss that results in dropped connections. My current suspicion is that thi... Anonymous fpga
AF 08:15 AM FPGA Development: RE: Ethernet PHY configuration and SSH access: Hi Zach,
Thank you for your reply.
I ran ethtool eth0 | grep PHYAD on my system, and it confirms that the PHY is detected at address 3, as shown in the attached screenshot.
Could you please let me know if the Ethernet hardware section... Anonymous fpga

ZM 05:40 PM FPGA Development: RE: Ethernet PHY configuration and SSH access: Hi Atef,
The image you downloaded should have an SSH server (OpenSSH) running by default, yes. @ps@ by default doesn't show all processes, which is why the grep in your screenshot didn't find it. Running @ps -A@ or @ps aux@ should con... Zachary Miller
AF 03:52 PM FPGA Development: Ethernet PHY configuration and SSH access: Hello,
I am working with a MitySOM-5CSx module on my own custom carrier board and I am seeing different behavior depending on which SD card image I use. I would appreciate your help to understand the correct configuration.
+*Hardware... Anonymous fpga

AF 12:47 PM FPGA Development: RE: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board: Thanks, it works. Anonymous fpga

MF 04:20 PM FPGA Development: RE: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board: Atef,
Can you make sure you have the MSEL set appropriately per the table below?
!image.png! Mike Fiorenza
AF 03:40 PM FPGA Development: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board: Hello,
I am trying to test bitstream encryption on a MitySOM-5CSx evaluation board and I am running into an issue during boot.
Here is what I have done so far:
In Quartus, I enabled bitstream encryption and generated an encrypted RBF ... Anonymous fpga

AF 03:57 PM FPGA Development: RE: Using the design security for MitySOM-5CSX: Hello,
I would like to encrypt the FPGA bitstream on the MitySOM-5CSX. I have been referring to Intel’s application note AN557 (Using the Design Security Features in Intel FPGAs) to understand how to enable bitstream (.rbf file) encrypt... Anonymous fpga

JI 12:43 PM FPGA Development: RE: Building the MitySOM-5CSX: Seth,
I got the GPIO pin on the FPGA side to work as you described. This is just as good as having an LED because the whole point was to have an example to study how the GPIO is triggered from the linux side,i.e. how the command "worms... John Iannuzzi

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Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V