Activity
From 02/12/2026 to 03/13/2026
02/27/2026
- DV 08:18 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Are you using the "Makefile":https://support.criticallink.com/gitweb/?p=mitysom-5csx-ref.git;a=blob;f=dev_5csx_h6_42a/Makefile;h=7d61fe6112ad18bf792a770dd3a5721078b5c475;hb=refs/heads/23.1-stable at the top of the FPGA proje... - XS 07:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your support, I build a envirment with Ubuntu 22.04 and Quartus 23.1; and finish re-build uboot. But when i try to generate SD image file, I got below:
$ make sd_image
scripts/kconfig/conf --synccon...
02/23/2026
- DV 08:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Boot *Makefile* (around line 40), *or* it could be related to your build environment: it looks like you're using our Ubunt... - XS 07:03 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang