Activity
From 11/19/2013 to 12/18/2013
12/16/2013
-
12:23 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
We figured it out last week. So we are fine with this for now.
Jack - MW 09:50 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- And... the capacitance requirements for any USB interface are *very* important. See the USB specification (usb.org) on the capacitance and in-rush current requirements. If you don't get these right, you may have trouble getting the HOS...
- MW 09:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Hello Helmut,
This is really an embedded linux question in general and not just a MityDSP-L138 specific question. But to get the OTG port to look like a mass storage device, you will need to enable the MASS STORAGE device gadget in ... - HF 09:36 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Thanks. I'm tasking my kernel guy on this. The link for RNDIS advice will be helpful.
HOWEVER, I would prefer it look like a mass storage device, so the host PC can directly access the embedded system's file system.
But when I se...
12/14/2013
- MW 08:38 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: 24bit LCD and Wifi module
- Not using the Development kit. Those pins are needed for the MMC / SDIO interface for the Bluetooth device as the pinmux options are selected.
It may be possible on your own custom board. The expansion kit needs an MMC / SDIO interf...
12/13/2013
- MW 02:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi,
To get the spidev device, you need to add an entry for it in your platform baseboard file.
See the recent "industrial I/O board platform file":http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=arch/arm/mach-d... - MF 01:40 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Nope. I don't see that either.
I am going with the low level register access for now. I have SPI driver code that ran on a C6748 and am porting that. You can gain access to the registers using mmap(). - GG 12:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
My guess would be that since in your baseboard file you set the modalias to "M25PE80" as part of the spi_board_info you will get a /dev/M25PE801.1 entry, or something to that affect, instead of /dev/spidev1.1.
Thanks,
\Greg
12/12/2013
- MW 06:56 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: ASADSn / ASREn pin loc
- EMIF_ASADS# is routed to Y16, bank 4.
-Mike
- Hi,
Is the EMIFA signal ASADSn/ASREn routed to the FPGA? If so, what is the pin location?
I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon Craven - LC 05:48 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Thanks
- MW 05:47 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
Here are the rest of the EMIF_AEA pin assignments.
-Mike
| NET | FPGA PIN | FPGA BANK |
| EMIF_AEA10 | AA9 | 5 |
| EMIF_AEA11 | AC11 | 5 |
| EMIF_AEA12 | AE12 | 5 |
| EMIF_AEA13 | AC10 | 5 ... - LC 04:48 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi,
Sorry, I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon - MW 07:08 AM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
While module are you using? Do you have a model number or a part number?
-Mike
-
05:17 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm still confused about this. Would it be possible to provide an example of multiple packets?
For example two packets each with a counter.
Thanks!
Jack - Hi,
Is it possible to use GPMC_AD8 to GPMC_AD15 pins to drive 24bit LCD and install/run WiFi 802.11 b/g/n with Bluetooth Expansion Kit at the same time?
Andrey - MC 06:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- Thanks Mike!
That was definitely the reason of the crash.
Thank you.
Michele
12/11/2013
- Hi,
In the supplied ucf files I can only find pin information for address lines i_emif_aea[9 downto 0]. I would like to use the other address lines. Are they routed to the FPGA? If so what are their pin locations on the FPGA.
Regar... - JC 04:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- The only things I see different in your circuit besides the removed 5V vbus switch(U101) are:
* Missing USB0_ID pulldown (R110)
* Missing capacitor (C119)
I'm not sure if either of these are required if using the port in periphera... - HF 12:17 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Jonathan,
Yes, we have a USB A connector coming from USB 0. So this should be akin to connecting a USB A to USB mini cable from the PC to the system. So I *should* be able to get this work. But no, there is not 5V being provided. ... - JC 11:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Mike, Correct me if I'm wrong.
"So maybe the question boils down to this. Can you plug a USB OTG device into a PC, using what kind of cable, and it all work itself out with the PC as host and the device as peripheral? If so, then I ne... - HF 11:03 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Michael,
Great. First, the P/N on my Critical Link baseboard actually matches the next to last, "80-000268RI-2 B". But if I need to make a revision to the board, I'll consult the last entry as you advised.
(((Please humor me whil... - MW 07:28 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Schematics for the industrial I/O base board are on this "wiki page":http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information. Use the most recent one.
There are 2 USB ports available. 1 only su... - HF 07:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Jonathan, I'll try those things. FYI one test case with a USB flash drive works for the critical link baseboard, but not our custom baseboard. I need to compare schematics. There may be something different, such as failure to provide ...
- MW 07:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- Hi Michele,
Set the CORE_INT_EOF_LEVEL to 1.
Our framework uses 2 levels (2 seperate GPIO interrupt lines between FPGA and OMAP-L138). By default, level 0 is used for cores managed by the ARM and level 1 is used for cores managed ... - MC 05:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- This is the crash dump on the serial output:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c5368000
[00000000] *pgd=c5312831, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000005 [#1] PR...
12/10/2013
- DG 09:27 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Hello!
If you have got console why don't you just copy files from your PC to board?
And another option - if USB host is available on the board, just connect a USB stick and copy files from it.
Make sure that something like
/dev/mmcbl... - DV 06:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with setting the go bit, the descriptor will be written on to this FIFO.
To send multiple packets you will have to push mul... -
05:18 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
Thanks!
Jack -
04:49 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it back to "1"?
I tried doing that but it didn't work.
Could you provide exactly what needs to be done to send multiple... - DV 04:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan -
12:17 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Thanks!
Jack -
12:12 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first address and not writing to the subsequent address that I changed to. Is there something else that I have to do to update th... - Dear Sirs,
I have to use a GPIO bank over FPGA to route some interrupts (let's say 8) through the fpga to the DSP.
For the purpose, I have used the call to tcDspFpgaGpio::ConfigurePin() method and subsequently SetISRCallback() method t... - PD 12:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Compiling the HelloWorld application with CGT
- Thanks Mike,
I will try that out. However for the time being, I am continuing with CCS on Windows. :)
Regards
Prashant
12/09/2013
- DV 03:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master when no other descriptors are buffered.
Yup, the address is part of the descriptor along with control signals.
For ... -
03:37 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
For our project, we have a signal (Data Ready) and whenever it goes to zero, there is a 16 bit data that comes in. I ... - DV 02:26 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells the SGDMA component where to write that packet to, so the second packet will stall until another descriptor is pushed onto... -
02:15 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be stored consecutively starting from the starting address.
But if that package is ended, and I start a second package ...
12/06/2013
- DV 03:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HSMC to GPIO
- Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan -
03:00 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: HSMC to GPIO
- Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera follows in their layout)
I attached the manual for the daughterboard.
Thanks!
Jack - MF 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- I don't see a SPI /dev/ entry.
Tried this (as in the example at https://www.kernel.org/doc/Documentation/spi/spidev_test.c) - GG 11:07 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
Reading and writing over a SPI bus on Linux is pretty simple. You need to open a file descriptor for the SPI /dev/ entry and use ioctl SPI_IOC_MESSAGE commands to send spi_ioc_transfer structs to the device.
Here's a for... - How do you read/write to a device on the SPI1 bus (CS1) on the ARM side? Is there an example? Can I do low level register read/writes or is there a driver?
I am using MDK_2012-08-10
I have recompiled the kernel with a custom base... - JC 09:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Once you have the network connection up you can easily move files using ssh and winscp.
- JC 09:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- It maybe of use to you to have the usb port act as a network device so you can send files over the network. See http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Enabling_USB_RNDIS_Support.
- I have inherited development responsibility for a custom base board using an OMAP-L138F SoM. I need to get USB working in one manner or another.
The cable designed by the board originator has a USB-A type plug on it, implying that ...
12/05/2013
-
06:14 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Beautiful Work! Thank you so much!
Jack -
05:57 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- O of course! Can't believe something simple like that slipped my mind.
Thank you so much! Hope this works!
Jack - DV 05:51 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
1) Hmm, I believe that error is from qsys generate not being run. Let me know if after running generate if that error still comes up.
2) Yes that is correct, it just needs follow the "Avalon Stream Standard":http://www.alt... -
05:35 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
A couple of issues:
1. I am having trouble compiling the code. It's returning warnings and errors like such:
Warning (125092): Tcl Script File mityarm_5csx_dev_board/synthesis/mityarm_5csx_dev_board.qip not found
Error ... - DV 03:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Jack,
I have created a new wiki section and have added the hps ddr example there. "LINK":http://redmine.criticallink.com/redmine/projects/mityarm-5cs/wiki/Writing_to_HPS_Memory
Dan - SH 02:59 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP software sometimes does not start
- Thanks for the reply Mike - I took a look at my code and the Debug outbound is created before the inbound in the DSP software. In any case, the problem "went away" - after a couple of glitches after first loading the software in the /mn...
- MW 12:37 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP software sometimes does not start
- I suspect that you may have a race condition between the ARM and the DSP setting up inbound and outbound message Qs.
The inbound message queues create local message q structures. The outbound message queues attempt to continuously a...
12/04/2013
- DV 08:23 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hey Jack,
My plan is to get it up Thursday afternoon. I currently have the FPGA side done but need to finish up the linux side and test it.
Dan -
05:18 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
When would you be able to make the examples available?
Thanks!
Jack - I have a strange problem with starting up some software on bootup. I have followed the instructions in this link:
[[http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/ARM_Software_FAQs]]
with a line that looks like... - GG 01:46 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Loading DSP-Code from Linux without DSPLink/DSPBios
- Hello Benedikt,
As far as I know, we've really only had experience running DSP code that uses the BIOS. Have you downloaded and looked at our MDK or our [[DSP Hello World]] starter guide? In the MDK we have a class called dspapp that... - Hej hej,
I have a coff-file with my DSP-Algorithm which runs perfectly when I start it via JTAG or via U-Boot. [Linux is up on the ARM in parallel. The communication between Linux and DSP is also working.]
Now I want to load the DS...
12/03/2013
- JC 04:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- I think that's the first step. The programs that have problems should then print error messages in the boot log. Might make things easier to take a boot log of the rw and ro boots to compare them so you can find the errors easier.
- SH 04:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- Yes, I was going to try just updating /etc/fstab and the bootarg environment variable and see if that works...what do you think?
- BD 02:48 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- Stephen,
Do you have an /etc/fstab in your filesystem? Have you tried updating that file as described in step 4?
-Bob
12/02/2013
- There is a discussion of how to set up a read-only filesystem in the following link:
[http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Configuring_a_Linux_Filesystem_for_Uncontrolled_Shutdowns]
but the instruction... -
04:28 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
We would like to use the HPS DDR as well, but as you can see from my numerous posts, we are really stuck on memory write to multiple addresses. So while you guys are preparing an example for writing to the HPS DDR, we will hav... - DV 04:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
Hmm, are you using the DDR SDRAM Controller with UniPHY in your QSYS project?
Also with this first release of the 5CSX SOM there is a special hardware modification that is needed in order to get the FPGA DDR to work, which... -
02:34 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
I don't see the TCL file that you are referring to. All the tcl files that I have are for HPS DDR not FPGA except for the one that you attached.
I attached the a print screen showing all the files.
Jack - DV 02:30 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
Did you also run the IO Standard TCL file generated by the tools?
Dan -
02:25 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
I ran the tcl script that you attached on this thread.
But when I tried to compile, it gives me errors like the following:
Error (169026): Pin FPGA_DDR_A[0] is incompatible with I/O bank 5A. It uses I/O standard 2.5 V, w... - DV 02:21 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
The IO Standard TCL file should be auto-generated by the tools.
To run it from Quartus:
1) Go to Tools->TCL Scripts
2) In the TCL Scripts window you should see multiple tcl scripts, there should be one that looks like mi... -
12:32 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
Could you provide the TCL file for the IO Standard as well please?
Thanks!
Jack - DV 10:52 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
I have attached a TCL file that will setup the pin assignments for the FPGA DDR.
Dan -
11:31 AM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: Link Down
- Hi Dan,
It happens while it's idling and booting up.
Thanks!
Jack - DV 11:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Link Down
- Hi Jack,
Is this while the dev kit is just idling in linux? Or is this just during boot up?
Dan - DV 11:03 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Have you taken the SDRAM FPGA port out of reset? The register is called hps.sdr.ctrlgrp.fpgaportrst, the description can be found in "HPS Addressmap":http://www.altera.com/literature/hb/cyclone-v/hps.html#hps.sdr.ctrlgrp.fpga... - MW 10:44 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: problem with spinlocks in linux kernel module
- Steven,
I think the reason why you see the difference is that your PC is likely a multi-core (multi-processor), on single core systems spin_lock and spin_unlock really don't do much for you because that is the only possible thread run... - Hi,
I tried to run a trivial test driver pasted in below on a PC using Redhat linux and on the ARM core of the OMAP-138 using Angstrom linux. The function "spinlock_test" trys to obtain a spinlock it has already by calling itself two ... - NK 12:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding developing real time application"
- Hi Mike,
We are planning UART from linux on arm9 cortex. Or can you suggest any feasible solution in this regard, as we are planning DSP only for image algorithms.
With regards,
Naveen K S
11/30/2013
- MW 07:34 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding developing real time application"
- Do you mean using a "UART from Linux":http://en.wikibooks.org/wiki/Serial_Programming/Serial_Linux? Or are you trying to use the UART with the DSP?
I'm afraid we can't help you design your application without detailed requirements.
... - Dear sir,
we are working on developing vision system, wherein we are using your mitydsp L138F SOM and Industrial I/o Board (as a sub system module in our entire system) for image processing. Our requirement is we need to interact with... - MW 07:29 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Driving DVI-D with Spartan6 LX45 Fpga
- The issue cannot be resolved without redesigning the PCB.
If you are using an LX-45, you cannot use the DVI interface on the dev kit. Why Xilinx did not bond out these pins remains a mystery.
I am sorry for any inconvenience.
... - From the following discussion, it is said that Spartan6 LX45 FPGA based MityDSP-L138F SOM cannot drive DVI-D on Industrial IO boards. Is this case true now also or this issue resolved??
Kindly reply as soon as possible.
Thanks in Adv...
11/28/2013
-
04:57 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: FPG DDR3 Memory Pin Assignment
- Hi,
Can you please provide the pin assignment for the optional FPGA DDR3 memory please?
Thanks!
Jack - MW 07:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding driving two displays using MitydspL138F vision development kit"
- The DVI interface on the L138F / Industrial I/O kit is DVI-D (see "wikipedia page about DVI interface types":http://en.wikipedia.org/wiki/Digital_Visual_Interface) compliant only.
To drive the displays you have attached using the VGA ... - "
ARM9 Based Platforms - Software Development: RE: "Regarding Driving Displays in MitydspL138F Vision Devlopement Kit"
Michael Williamson
If both the LCD display and the display connected to the DVI interface can run using the timin...
11/27/2013
- MW 08:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding Driving Displays in MitydspL138F Vision Devlopement Kit"
- If both the LCD display and the display connected to the DVI interface can run using the timings (e.g., same resolution, same pixel clock rate, same front / back porch settings, same vertical refresh rate) then you should be able to run ...
- Hi sir,
Initially our requirement is to drive two displays in MitydspL138F VDK.
In Mitydsp L138F based vision development kit datasheets it was given LCD panel interface and DVI interface are provided. Can we drive two displays bot... -
05:07 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I can't find any info so I would appreciate your help.
I can get data stored in one location of the memory. But when I...
11/26/2013
-
04:37 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi,
Can someone please get back to me on this?
Thanks!
Jack
11/23/2013
- MW 03:34 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- You can do it in the DSP using tcDspSyscfg::SetMasterPriority() in the dsp core library.
-Mike
- SH 01:30 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- Thanks for those suggestions, Mike. According to Table 11-2, the default priority for EDMA is 0 (highest) and for ARM instruction and data is 2 (lower). When I look at these registers in debug mode (DSP), I see these default priorities...
- MW 08:40 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- Hi Steven,
Is the DMA priority configured higher than the ARM data access priority in the Master Priority Configuration registers (see the OMAP-L138 Technical Reference Manual regarding DMA bus mastering priority)?
We have seen FPG...
11/22/2013
- I'm seeing some errors similar to those mentioned in the following thread:
http://support.criticallink.com/redmine/boards/12/topics/2954
I am using the CL FPGA modules for EMIF, etc with no changes and making DMA transfers from the FP... - GG 05:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
Perhaps the project was corrupted when you upgraded it to the 13.1 tools. I've attached a copy of the project that has been successfully upgraded to build in the 13.1 tools.
Let us know if you have any issues.
Thanks... -
03:29 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Mike,
Can you provide for me the exact product number for the Micron SDRAM on board. I need information on the timing parameters for those memories.
Thanks!
Jack
11/21/2013
-
02:10 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Greg,
I am using 13.1 Quartus, and I ran the script that you recommended and the error that I sent you was what I got after I ran the script. So it's not from the compiling part, but just the script.
Thanks!
Jack - GG 02:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
Are those the same errors you were receiving before? And typically when Quartus reports an error there is a plus symbol next to it that you can use to expand the error message and get more details. Could you provide us with ... -
12:35 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: Quartus II Subscription Edition Error
- I tried running the tcl script and it didn't work.
The errors are:
Error: Quartus II 64-Bit TimeQuest Timing Analyzer was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 368 megabytes
- GG 09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
What version of the Quartus tools are you using?
That project was built with the 13.0 sp1 tools. If you've updated it to the 13.1 tools you probably need to run the hps_sdram_p0_pin_assignments.tcl. Select Tools -> Tcl Sc... - MW 07:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Compiling the HelloWorld application with CGT
- You should dump out the full build texts between the two operations and compare.
I suspect that the memory configuration templates (which define the shared regions for DSPLINK) are somehow not the same between the 2 builds.
-Mike
- MW 07:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- HI Jack,
I suggest you head over to the "Cyclone V Documentation page":http://www.altera.com/literature/lit-cyclone-v.jsp Altera web site for this information.
The documentation is extensive, and should provide the information you ...
11/20/2013
-
06:25 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: HPS Memory Controller
- Hi,
Could you guys provide some documents and timing diagrams for the HPS memory controller?
Thanks!
Jack -
04:53 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Link Down
- Hi again,
I have the ethernet connected to the development kit, but on the console it kept on giving me the following"
libphy: stmmac-0:03 - Link is Up - 1000/Full
libphy: stmmac-0:03 - Link is Dowwn
Repeated for a few seconds. B... -
03:51 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Quartus II Subscription Edition Error
- Hi,
I am using the mityarm_5csx_dev_board project that you guys have. If I use the web edition of quartus to run it, everything is fine, but if I use the subscription edition of quartus ii I get some errors.
First of all, when I op...
11/19/2013
-
05:49 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Ethernet
- Hi,
How can I configure the FPGA such that the ethernet will still be functioning after I program it. I notice that the ethernet is down after I load the fpga.
Cheers,
Jac - MW 05:25 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clock
- There is a 25 Mhz clock brought in on the main HPS_CLK1 input (pin E20). It's actually defined in the Qsys HPS component of the reference project. Qsys automatically connects the HPS clocks during the build process. You can route this...
-
05:18 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Clock
- Hi,
Where is the clock on the MityArm?
I am using your mityarm_5csx_dev_board project, and it's not there. Could you provide me the pin assignment for your clock please?
Thanks!
Jack