Activity
From 06/18/2014 to 07/17/2014
07/17/2014
- DV 05:08 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we pushed a patch to our git server about a week ago that should of addressed that issue, patch: http://support.criticallink.co...
- PB 03:42 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format.
For the rootfs tarball, I intended to do what you proposed but I wasn't selfconfindent. Your post helps me !
Kind ... - ND 09:13 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- I am currently working through the kit and having a similar experience. The following seems to work for me in regard to your yocto question.
Add the files from the modules image to the core image - same directory (lib/modules/3.12.0-x...
07/15/2014
- PB 06:28 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at u-boot time. OK
I still have open questions, among them :
- I'm unable to recreate the dtb file I can find on the... - NP 04:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Jonathan,
Thank you for your patches, it's working for me!
I have applied and successfully rebuilt my kernel.
And almost PRU example from TI can run on my board.
Thanks you very much! ^^
_Regard,
Manh BT
07/14/2014
- JC 11:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Ngoc,
Can you confirm that this is working for you and i'll move the changes into our main kernel branch?
I also created a wiki page to help future projects [[Using PRU]] - JC 10:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- gpioToggle test passed when i just ran it. Not sure why.
- JC 10:24 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Reran some of the commands to see which fail. The ./PRU_memAccessL3andDDR can cause system segfaults as it appears to use a fixed part of ddr during its test and if a program or linux happens to be residing there then it will be overrid...
- JC 09:11 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Running through all the examples, atleast one of them seems to have caused a system segfault as not even reboot was able to run afterwards.
- JC 09:09 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Ngoc,
I have been working on getting this to work. So far i've integrated the patches which i've posted to a test branch until we can confirm its working. Please checkout 'mitydsp-linux-v3.2_pruss_wip' branch. Currently it is cr... - NP 04:45 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
Thank you, I'm waiting for your patches. ^^
Regards,
Manh BT - JC 09:43 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Yeah by using the ti_ 335x include files I was hoping to greatly simplify our config file. Hopefully it hasn't caused more confusion then it needed to.
-
09:31 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Ok,
I knew it had to be in there somewhere, was just a bit confused
as the original mityarm335x.h had a nice section in the file for all
that.
Thanks,
John C. - JC 09:26 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Pretty sure I found "#define CONFIG_SPI" in one of the ti_ config files that get included.
-
09:25 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Yes the Micron N25Q00AA does support the 48Mhz clock. The sf erase still seems longer
but I'll need to time it get get more specific. I did notice that the mityarm335x.h
file was missing "#define CONFIG_SPI" as I though it was needed ... - JC 09:25 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I have been looking into this. It seems that it was a mistake as the added resistor isn't mentioned in our Engineering change request. I noticed the added resistor recently when I was working towards getting the OTG feature working. C...
- SE 03:28 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- OK, the cable that I used was a miniAB to USB A plug which was then attached to a USB A to USB A gender changer (a little crude, but it works).
Dare I ask why did you add a pull down resistor on your revision C board if the specificat...
07/13/2014
- BD 10:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hello Manh BT,
The patches Mike described are in the mainline Linux kernel (http://kernel.org/). You can search for those commit hashes via Google to see the required changes.
We are in the process of applying and testing these pat... - NP 09:42 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Michael,
Thanks for your information, but where can I get above patches? Is it in Critical Link MDK ?
Regard,
Manh BT
07/11/2014
- JC 05:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Also make sure your Nor chip supports 48Mhz on the spi bus.
- JC 05:25 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Did you notice any time difference with the slower speed?
-
03:30 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- I took out the CONFIG_SPI_FLASH_BAR define and it now seem to pass the long erase command.
-----------------------------------
U-Boot# sf probe 0:0
SF: Detected N25Q1024 with page size 256 Bytes, erase size 4 KiB, total 128 MiB
SF:... - JC 02:23 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It may be perfectly fine with the generic name then.
Try changing the spi clock speed and see if you get different results. I found with the nor on our SoM the erase seemed faster when run at 1Mhz but the write was much faster at 48M... -
02:19 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- I added the CONFIG_SPI_FLASH_BAR define to mityarm335x.h and the warning is goes away on the "sf probe" command.
I added the #UNDEF and then "#define CONFIG_BOOTDELAY 3" to mityarm335x.h, and this now works.
The "sf erase" command seem... - JC 01:38 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- 1) I'm not sure why its detecting it differently. Maybe the newer u-boot has a more specific driver for this chip?
Also from the README -
12:44 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Hey Johnathan,
Testing out the new spi bus changes seem fine. I do have two quick questions:
1) The original code I wrote spit out the device ID as:
-------------------------
U-Boot# sf probe 0:0;
SF: Detected N25Q00AA with p... - JC 01:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- As per the On-The-Go spec, the mini USB adapter is supposed to tie the USB_ID pin to GND to indicate it should be put into host mode.
http://en.wikipedia.org/wiki/USB_On-The-Go#OTG_mini_plugs
http://www.amazon.com/Host-Cable-fema... - SE 12:36 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- Yep, loading an image seems to be OK. Next week I'll try the whole image + rootfs and make sure that works too.
Thanks! (sometimes you just need a nudge in the right direction!) - SE 12:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- OK, now I get it. There's no resistor on my board pulling the ID pin down to 0V. I've just put a link between pins 4 & 5 on J100 and its all OK now.
I'll try putting an image on there for it to boot from and let you know. - SE 12:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- The number is 80-000286RI-2
REV B
S/N 132556
Which bootloader are you using? I've been using my own compilation but that is wholly based on the one taken from the Git repository from your wiki link with no modifications. - JC 12:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- Whats the part number of your dev kit? Should be a 80- number.
- JC 12:03 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I just tested this by first plugging the flash drive into the full size usb port J102. With no luck. Then plugged drive into J100 via adapter cable and it was discovered. See log below.
- SE 11:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I forgot to say that I know that the USB port works because, once in Linux I can mount the drive OK and read/write files etc.
USB drive is plugged into J100 via an adapter cable. - Hi there,
I'm using the L138F SoM on a REV B Industrial I/O board and I am trying to boot from a USB drive. uBoot is configured for USB but when I try:
@usb start@
All I get is:
@(Re)start USB...
USB: scanning bus for devic... - ND 09:34 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building u-Boot and Preloader
- I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/mitysom-5csx, is that correct and is there anything else that needs to be copied?
Thanks,
Nigel.
- MW 08:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
I think we need to add the following patches (from linus tree) to the kernel to instantiate the PRUSS drivers for the L138.
2eb2478d471e45e1d0c8bb3defbf82bf7204e13d uio: uio_pruss: replace private SRAM API with genalloc
8e0d72... - Hi everyone!
I'm using MityDSP-L138F SOM + IO Industrial Board and now trying to work with PRU subsystem of OMAP-L138 processor.
I've found some instructions from:
http://processors.wiki.ti.com/index.php/PRU_Linux...
07/10/2014
- JC 05:10 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- The skipping bad block is not an error but more of an info. Blocks can be marked bad from factory and during use. This is just telling you one was found and skipped over.
- BJ 04:19 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- The clock is working now. Thank you.
But when we flash the nand, there is an error:
root@mityarm-335x:~# flash_erase /dev/mtd7 0 0
Erasing 256 Kibyte @ 400000 -- 80 % complete flash_erase: Skipping bad block at 00440000
Erasing 2... - JC 03:29 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- So if this is the problem I'm thinking of. It was discovered that when we changed to the 3.2 kernel we weren't setting up the RTC and by default the RTC was using its internal clock. This clock has a much higher error than the external...
- BJ 03:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Hey Jonathan,
Thanks again, we will definitely try this solution and let you know if it works. I would like to know what you think was the problem; it is still unclear to me if the clock on the processor chip is bad, or the kernel was... - JC 03:00 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- I've attached the lastest uImage but yes you can build it if you would like. Instructions are here [[Linux_Kernel]]
This should be built from git commit: e53da3cda4dba6464b5b612e865c29e93144957f - BJ 02:57 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- NAND read: device 0 offset 0x340000, size 0x500000
Skipping bad block 0x00780000
5242880 bytes read: OK
## Booting kernel from Legacy Image at 80007fc0 ...
Image Name: Linux-3.2.0+
Image Type: ARM Linux Kernel Image (unco... - BJ 02:56 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- We used the pre-build kernel image that came with the board. The kernel that in the Virtual Machine/home/mitydsp/project/linux-mityarm-335x is already updated through git. I will post the boot log below. Is this fix need us to rebuild th...
- JC 08:12 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- What version of the kernel came with your devkit? Could you post a boot log?
Particularly I want to know if your kernel is new enough to have this fix. http://support.criticallink.com/gitweb/?p=linux-mityarm-335x.git;a=commit;h=7fae5... - ND 02:23 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Breaking changes on early MityARM
- Should have spotted that note but somehow managed to miss it!
Thanks,
Nigel. - MW 02:00 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Breaking changes on early MityARM
- Hello Nigel,
Sorry about that. The description of the hardware changes for the Dev Kit baseboard are here:
https://support.criticallink.com/redmine/projects/5csxbase/wiki/Errata_and_Product_Change_Notifications
The only signifi... - I have an early MityARM module and dev kit. On trying to implement the latest software versions I found that the Ethernet interface was not functional. On investigating it appears that there has been a pcb change on the RGMIII_RESETn sig...
- I am just revisiting the development kit after working on other projects and I am trying to locate the copy_files.sh script that is referenced on the building u-Boot wiki page.
It is not in the tools/scripts folder, or anywhere else t...
07/09/2014
- JC 05:12 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Just pushed a fix for this.
http://support.criticallink.com/gitweb/?p=u-boot-mityarm-335x.git;a=commit;h=82762ccda7286bcc7a72b51b087b3ad6742d8a5f - BJ 04:33 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Here is our clock tree (in /sys/kernel/debug/clock/summary):
clock-name parent-name rate use-count
ehrpwm2_tbclk none 0 1
ehrpwm1_tbclk... - BJ 04:14 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- When we boot into Linux and use the "date" (system clock) and "hwclock" (RTC I assume) commands to set/ask for time, we notice that the time changes by an hour / day (from what the actual time should be). So, for example, if we set both ...
- MW 08:02 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Hi,
What do you mean by "hardware and software" clocks. Are you using the RTC or just the system clock? Can you dump your clock tree?
Are you running a heavy processor load or kernel module that may be blocking interrupts?
Nor...
07/08/2014
- Hello,
We bought a MityARM335x dev kit months ago. We have noticed that the time on the board (both software and hardware clocks) drifts by about 1 hour per day. Is this a common problem? Did we get a defective board? Are there any kn... - Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I understand from the errata sheet that the identified issues are not a problem for me (FPGA DDR, QSPI Nor, RVB LED).
I have...
07/07/2014
- Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interface?
Thanks.
07/03/2014
- AD 05:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the rest of the Critical Link modules.
- Adam - BL 05:05 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi,
I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd_image_mitysom_5csx_rev1B.bin of=/dev/sdb bs=1M" into a brand new 8GB MicroSDHC sd card. Next, I typed "sync" as instruc... - UF 02:45 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- It was a cache invalidation issue. Calling BCACHE_wb() solved the problem.
I did find a small bug in the trasmit() code: - DR 08:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- My first thought on seeing this is that it is probably a cache issue. After you set the values in the buffer, the values are in the cached version of the buffer, but haven't be written to external RAM. When you do the DMA, it doesn't g...
- SB 11:16 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- I got a similar problem reported here.
https://support.criticallink.com/redmine/boards/8/topics/4002
Can someone help me?
Silvano - Dear all,
I have a problem with Code Composer 6 and my DSP/BIOS project (called "quadra").
I have a first file (called "main.cpp") with the main() and a reference to a simple empty function defined in "pippuzzo.h" and called _dataIO(...
07/02/2014
- AB 09:27 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on this wiki page (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image) in the "Develo...
- BL 06:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Mike,
I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register somehow shows "0x00000000". So, I set it to 0x7, then 0x6, to make sure the hps2fpga bridge get reset and release the reset.... - MW 08:52 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- For reference on the reset register:
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/register_rstmgr_brgmodrst.html
- MW 08:51 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
It looks like you are using version 3.8 of the kernel. Version 3.8 does not have the FPGA bridge drivers that provide the sysfs layers.
I believe we are now shipping DevKits that use a 3.12 version of the kernel as the ba... - UF 06:47 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- We cannot get the uPP to work. For test we just use the FPGA to pass the uPP pins to FPGA output pin. The Enable pin works fine, but the Data pins make no sense. Attached is an image showing the Enable pin in pink and a data pin in blue....
- MW 07:19 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Ah, yes, I am sorry I forgot about the EMIFA scheduling delays. You are correct.
If you are using the reference Platform.tci DSP/BIOS configuration from the BSP, try the "IRAM" section.
I believe the L2 (256K total) is setup as 1... - UF 12:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- We started with EMIFA. We got a delay of 11uSec between transfers as discussed in this post:
https://support.criticallink.com/redmine/boards/12/topics/3903?r=3942#message-3942
This seems way slower than your expectations. Removing ... - SB 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Thanks a lot to everybody.
It was a simple linker problem.
Silvano - Hello everybody.
We see an unexpected behaviour during simple debugging operations.
/*
* main.c
*/
#include <stdio.h>
#include <std.h>
#include <log.h>
#include "testcfg.h"
int pippi[1000];
Void main(void)
{
shor...
07/01/2014
- JC 04:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Note i found the generic c674x device under target: generic devices
!DSP_C674x.png! - GD 03:39 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Silvano,
Have you followed our guide to building a Hello World application?
https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World
The steps for setting up a proper build environment and building D... - Dear all,
we are trying to build a simple application on DSP using Code Composer 6 plus DSP/BIOS.
In the following the very simple code:
/*
* main.c
*/
#include <std.h>
#include <log.h>
#include <stdio.h>
#include "Testcf... -
09:49 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- U-Boot# sf probe 0:0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 1:0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI... -
09:49 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Jonathan,
I checked with manufacturing and they do use the command in verification
of basic communication with the SPI flash. So would it be possible to get the
sf command into the main line again? My testing shows that with th...
06/30/2014
-
05:06 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Following your lead and my hardware engineers suggestion we did a temporary check and set 0x44E00050
(CM_PER_SPI1_CLKCTRL Register)to a 0x2 (it was a zero) to enable the SPI1 clock. Our system came up
and is running. I'll try and fix ... - JC 05:03 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Committed change.
http://support.criticallink.com/gitweb/?p=u-boot-mityarm-335x.git;a=commit;h=bc7833792442421a60e74ef2dc871429b34448fe
Tested in u-boot. - JC 04:54 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I'm testing this change right now and am going to push a commit if it works.
-
04:48 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Thanks. Let me take a look and if it works.
- JC 04:45 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I think I found the problem. The memory address 0x481A0000 refers to McSPI1 and only spi0 is enabled in the u-boot.
In the following file in the enable_basic_clocks function:
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
You should be... -
04:40 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- We had originally set up to boot out of SPI NOR and on occasion do use that ability for
manufacturing testing. The biggest thing at this point is trying to resolve why we have
a SPI bus dependency on the old u-boot. - JC 04:16 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- No since booting from the spi nor on our SoMs doesn't work and I wasn't aware of anyone using the nor, I didn't look into getting it functioning in u-boot. Do you use the spi nor?
Looking at board/ti/am335x/board.c it looks like TI a... -
03:40 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Hey Jonathan,
Looking at your release without any of my mods, serial NOR was removed (no sf commands.) Was there
anything specific as to why it was removed? When I enable the SPI, I do get the sf commands back but they
are unstab... - MW 04:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Have you tried just writing to the FPGA via EMIFA? That would be a 16 2-byte word transfer. Even with 10 wait states (using 100 MHz EMIFA bus), that would be < 2 usecs. I think by default we use 5 wait states with address demuxing opt...
- UF 03:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Re-architecting our code is not really a vaiable solution. We have a feedback loop running in the DSP, that depends on data that should be read from the FPGA and be used to generate the next packet. The DSP loop is too complicated to be ...
06/28/2014
- GG 04:22 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Hello,
First of all, using such small packet size you may not be able to completely eliminate the delay between sending packets. There is an overhead associated with programming the uPP DMA engines. So, you may want to consider the p...
06/27/2014
- BL 09:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Mike,
I attached 2 files as you indicated in your previous reply. One is boot.log and another one is foo.txt.
Let me describe my intention and building flow to you.
1. I have a function need to be implemented in FPGA with HPS b... - MW 07:56 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- If you can't see the enable file then the driver for the device isn't compiled in or the device tree blob doesn't instantiate it. You typically don't want to enable the bridge until the FPGA is loaded.
Can you attach your full boot l... - We are trying to use uPP to send data from the DSP to the FPGA. The problem is that there is a delay of about 8 micro seconds between packets being send.
This is the code we use in the DSP: - JC 08:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It's possible or even probable that name of the pound defines changed in this version. You can check the Readme to see if they are listed otherwise might need to grep for them.
Also take notice that at the end of the config there is ... -
04:41 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Hey Jonathan,
Do I only need the "#define CONFIG_SPI"? I've tried that along with (from the original mityarm35x.h)
the following no luck:
/* SPI support */
#ifdef CONFIG_SPI
#define BOARD_LATE_INIT
#define CONFIG_OMAP3_SPI
... - JC 04:29 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It does look like SPI was not enabled in the new u-boot config. Checkout the differences in include/configs/mityarm35x.h between the new and old. This was done since u-boot doesn't need access to any spi devices so we left it up to lin...
-
02:36 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: SPI clock issues with using newest u-boot
- After moving to the newest u-boot we are having issues running SPI bus. Accessing the McSPI registers (0x481A0000) causes a data
abort. This suggests that the clocking is no longer set up correctly and that we have a dependency on u-boo...
06/26/2014
- BL 10:46 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Thanks for your reply.
I am currently intend to use hps2fpga bridge only in my design. And I just copy the generated rbf file into SD card and loaded it into FPGA by using "cat file.rbf > /dev/fpga0". By refering to the 2nd link from ... - MW 08:12 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Which AXI crossbar interface are you using? The hps2fpga bridge or the lightweight bridge? Did you make a new preloader?
Ref: http://www.altera.com/literature/hb/cyclone-v/cv_54005.pdf
You must ensure that you are enabling the br... -
01:00 PM
MitySOM-5CSX Altera Cyclone V
Software Development: UART RS232
- Hi,
Could you point to some examples for UART RS232 communication?
Thanks,
Jack - BD 11:22 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SSD on MityDSP-L138F
- Hannes,
As mentioned in the errata, they do not recommend the "reset" approach because they cannot guarantee that it will work in a reasonable amount of time.
If you are going to go down this path, I suggest you test this approach ... - JC 08:25 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Where to download the document about Memory Map and Register Address of IO Board 80-000268RI-2C and OMAPL138F
- These are provided by TI. You can find them here: http://www.ti.com/product/OMAP-L138/technicaldocuments
You should start with the "OMAP-L138 C6000 DSP+ARM Processor (Rev. H)" Datasheet and the "OMAP-L138 C6000 DSP+ARM Processor Techn... - MW 08:16 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Where to download the document about Memory Map and Register Address of IO Board 80-000268RI-2C and OMAPL138F
- The memory map of the OMAP-L138 can be found on TI's main "OMAP-L138 web page":http://www.ti.com/product/omap-l138 (see the datasheet and the technical reference manual).
Not sure if that is what you are looking for.
06/25/2014
- only some brief documents are found in wiki,
Where can I download the document about Memory Map and Register Address of the IO Board 80-000268RI-2C and OMAPL138F? - Hi,
I have implemented a logic and loaded into cyclone V FPGA. Before that, I did run simulation to access a memory, which was generated by Megafunctions Wizard and is inside of FPGA. After I loaded the image of my design, I need to f... - JC 05:09 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Dirty gets appended to the version string for both u-boot and the kernel when you compile source code that has changes that aren't committed in git. Its a sort of warning to the developer that this version may not be reproducible from a...
-
05:05 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- I pulled the AM335XPSP_04.06.00.08 tag and there were a lot of differences. I don't think it matters
that much as we really only modify six files of yours, and most of that is because of the one very
large SPI NOR chip that we need. I'... - JC 04:58 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Looks like both the 03 and 08 branches have the same 2011.09 date so harder to determine which branch of code you were using.
- JC 04:55 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- You were likely using the code from the AM335XPSP_04.06.00.08 branch before and now should be using the u-boot-2013.10 branch. There may be alot of changes between the two branches.
-
02:05 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Hey Jonathan,
Can you tell me if I were to pull a full u-boot "tree" from your "u-boot-mityarm-335x.git/tree", which one of
the head labels should I use? u-boot-2013.10, AM335XPSP_04.06.00.03 or AM335XPSP_04.06.00.08 ?
I'll... -
12:18 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Seems like when I used our NAND mlo/u-boot burn in scripts, I blasted over the old u-boot by erasing NAND from 0 to 0x1E0000.
Sorry for the distraction. -
12:11 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Not sure what happened, but even placing the original MLO back it will not boot:
U-Boot SPL 21401-101.01.00.02-dirty (Nov 06 2013 - 08:59:11)
Texas Instruments Revision detection unimplemented
MityARM335x profile 1 - Model No: 3352... -
12:02 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Booting from the mmc card now does not show that u-boot in NAND has any issues.
U-Boot# nand read 8d000000 80000 1e0000
NAND read: device 0 offset 0x80000, size 0x1e0000
1966080 bytes read: OK
U-Boot# - JC 11:56 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Yes we decided to store everything in nand using the correct ecc so we disabled the nandecc command. So you do not need to change ecc modes anymore in u-boot.
Odd I wasn't aware of any compatibility problems with loading the old u-bo... -
11:43 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Looks like we can't reach u-boot with the new MLO. We see the following and then it stops. If we plug in the
mmc, we are back. Any suggestions?
John C.
U-Boot SPL 2013.10-gd35e056 (Jun 03 2014 - 17:00:30)
MitySOM335x profile 1 -... -
11:34 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Thanks Jonathan,
It seems the u-boot nandecc command has changed. We used to run the following script for
burning all four MLO locations. When we ran the "nandecc hw 2" command it used to come back
with a "HW ECC BCH8 Selected" r... - JC 11:17 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Okay. I created a FAQ about this issue incase anyone else runs into it.
https://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Software_FAQs#U-boot-has-started-hanging-on-startup-while-booting-from-nand-or-is-behaving-... -
11:13 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Hey Jonathan,
Yes there is indeed an error. I'll try the newer MLO to see how that works.
Thanks,
John C.
U-Boot# nand read 8d000000 0 80000
NAND read: device 0 offset 0x0, size 0x80000
524288 bytes read: OK
U-Boot#... - JC 10:18 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- If you confirm there are bit flips you can then flash just the UBL into the NAND and see if it boots fine. You'll see something like the following during boot to show that its correcting the bit flips.
- JC 10:13 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Try doing to following. It should print out bitflips if it finds them.
-
09:53 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Hey Jonathan,
I don't have access to a booted Linux, only u-boot. I created a text script that runs the u-boot "nand dump <address>" from address 80000h to F0000h in increments of 800h = 2048 (page size.) The output is raw (see inc... - LY 04:02 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: DSP to FPGA SPI Setup Question
- Hello,Mike
Thank you very much.
- MW 12:42 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: DSP to FPGA SPI Setup Question
- What is your target update rate? Continuous?
You might try first to rip out all of the overhead on the tcDspFpgaSpi.cpp code (there is LCK_pend()/LCK_post() for serialization control, etc) and boil it down to the register writes.
... - LY 11:32 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: DSP to FPGA SPI Setup Question
- Hello,Mike
Thank you for your help.
I have attached two pic
----one is the SPI bits transfer rate(This is our desired speed),
----another one is the word to word transfer rate(This is slow. We want it can be fast,Could you give u... - MW 10:47 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: DSP to FPGA SPI Setup Question
- Can you check with a scope at what the clock rate is on the SPI device, and the interword write delay? I just want to confirm they are getting 50 MHz clock rate.
It might be the EMIFA transfer, but we should confirm that the SPI de... - AB 10:39 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: DSP to FPGA SPI Setup Question
- Update and followup question from the customer:
We have made the SPI work, but transmitting the word to word is slow.(about 11 uSec to send a 24bit word).
This is the code we run in the DSP:
spi = new tcDspFpgaSpi((void *)my_bas... - MF 12:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Interrupting the ARM from the DSP
- Thanks. This does what I wanted.
On the DSP side: - MW 09:11 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Interrupting the ARM from the DSP
- I think that you are confusing signals and interrupts a bit.
You need to write some kernel module code to register an ISR handler for the CHIPSIG (which may already being used by DSPLINK) and forward/create the signal condition you ar... - MF 08:26 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Interrupting the ARM from the DSP
- Yes, I am familiar with DSPLink and am using it. However, I have time requirement that DSPLink cannot meet. Polling uses too much CPU time. Interrupt would be the most efficient. I just need to know how to connect the CHIPSIG interrup...
- HK 08:01 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- There you are. Note that i had to change the initialization in the code as noted above.
- MW 07:26 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- If you don't mind, could you post your config.gz file?
- HK 05:37 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hey again,
i tried changing it from DMA to PIO. Now, everything seems to work. Device is readable, writable and mountable. Performonce is ok - about 8MB/s either way.
The ethernet problem is gone. I'm not sure where the problem was... - Hey folks,
I'm trying to use a SSD instead of a HDD on the L138F.
I found in the errata that the OMAP-L138 has a problem with SATA devices capable of SATA 3. I'm using a Samsung 840 evo.
The kernel detected the disk once, but ... - AM 02:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Jonathan, thank you, I will track your branch.
06/24/2014
- GG 05:41 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Interrupting the ARM from the DSP
- Hello Mary,
I'm not sure what the problem is in your specific example as we almost always use DSPLink to to communicate between the ARM and DSP. We have wrapper classes that allow for passing messages between the DSP and ARM, and uti... - I would like to have the DSP (running BIOS 5) interrupt the ARM (running Linux MDK_2012-08-10)
In the DSP Code: - JC 05:19 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- That is what I'm suggesting. You can verify if this is the issue by running the 'nand dump' or 'nand read' command and looking for any reported fixed bitflips.
Note you can try this from linux as well. The -n option should allow you... -
05:07 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- So let me try and clarify the issue. We have been running our u-boot for about 10 months with no issues. Are you suggesting that a bit has gone bad and because the older MLO did not set ecc correctly, we are now seeing this strang behavi...
- JC 04:56 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Those ecc errors are coming from reading the environment from nand. If I remember correctly the older u-boot saved the environment using a 1 bit ecc (hamming) instead of 8 bit ecc (bch-8) which the new u-boot uses for everything. You ca...
- JC 04:49 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- No nevermind, thats not correct. You do have a 256MB nand module. So the first u-boot should be correct.
- JC 04:47 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- U-Boot mainline:
origin/u-boot-2013.10: d35e05656457c2d3715de8c3eb7c777375c160ae
u-boot config: mityarm335x_4kpage_config - JC 04:46 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Woops hangon didn't notice that you had a 3352 module. They have a larger nand and require a special u-boot build.
-
04:40 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Hey Jonathan,
Something is very unhappy. Here is the boot:
CCCCCCCC
U-Boot SPL 2013.10-gd35e056 (Jun 03 2014 - 17:00:30)
MitySOM335x profile 1 - Model No: 3352-GX-X27-RC Serial No: 134253
Configuring for 256 MB DDR3 @ 400MHz
C... - JC 04:28 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- There was a bug with the older u-boot where ecc was not enabled when the UBL loaded the u-boot image. This meant that bitflips could cause weird error messages. Seeing as you don't have any problems when the u-boot is loaded from mmc, ...
-
04:22 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- Here is the boot sequence:
----------------------------------------------------------------
U-Boot# CCCCCCCC
U-Boot SPL 21401-101.01.00.02-dirty (Nov 06 2013 - 08:59:11)
Texas Instruments Revision detection unimplemented
MityARM335x... - JC 04:14 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- John,
What version of U-boot are you using? If you can include the full bootlog that would be helpful. -
03:59 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- As added information, the mtest command works.
Commands that *do* work:
mtest 402fffe0 402ffffe A5A500FF
mtest 80000000 8d000000 A5A500FF
Commands that *don't* work:
mw.b 8d000000 A
mw.b 402fffe0 A
mw.w 402fffe0 A
mw.l 402fff... -
03:24 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: MityARM335x profile 1 - Model No: 3352-GX-X27-RC failing memory writes in u-boot
- We just received one of our units back from the field and it hangs running a "mw.b" command in the u-boot param script. The system will lock up using DDR or internal ARM memory addresses in the mw.b command. If we boot off the mmc sd car...
- JC 12:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Andrey,
Not sure if its any help but I've pushed a work in progress 3.14 branch to our git. Its based off the mainline 3.14.y branch. Haven't been able to get SPI working so the ethernet isn't getting initialized as its configured fr...
06/23/2014
- ES 10:25 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- All unused connections are no connects.
- ES 09:59 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- I have attached a plot showing the rise of the supply on the baseboard (channel 2) and the Mity card (channel 1). As you can see there is a droop in the supply on the card. I assume there is a switch mode regulator to generate the 1.8V f...
- MW 09:54 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- What are you doing with unused connections on the module?
- ES 09:52 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- It remains hot until the next power cycle. A reset cycle alone does not give an improvement.
- MW 09:15 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- On non-FPGA variants, DVDD3318_A, DVDD3318_B, and DVDD3318_C are all tied to 3.3V.
Does the issue only occur during reset, or once the unit boots it remains "hot" until another power cycle or reset cycle? - ES 09:07 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- All our I/O to the card is 3.3V. The OMAP processor has 3 configurable power groups which can be connected to 3.3V or 1.8V. I believe you have them all connected to 3.3V but as I don't have your circuit I cannot verify this. Could you co...
- MW 07:56 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- Ok.
I suspect the issue may be related to I/O voltage levels (you have I/Os being driven or pulled to a value larger than the bank voltage), or during reset the OMAP-L138 typically pulls most of it's I/O pins (internally) to +VDD of w... - ES 07:51 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- We are using a baseboard developed for our application. I'm happy to share the schematic. Let me know how to get that to you. The variant we are running is without the FPGA.
I have managed to measure the excess current draw. When it i... - MW 07:06 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 processor running hot
- Hi Ed,
Are you running on a DevKit or on a custom board? Would you be willing to share your schematic (privately to CL, not via this forum page)? Are you using an FDGA variant or processor only variant of the module?
-Mike
- We are some way into the development of using the MityDSP-L138 platform. I recently noticed that about 50% of the time when the module is powered up the OMAP processor runs very hot, >50C. The other 50% of the time it runs relatively coo...
06/21/2014
- AM 03:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Jonathan, nothing special only setup kernel config (attached).
I use Yocto Project Daisy toolchain and kernel from git://git.yoctoproject.org/linux-yocto-3.14.git, branch "standard/base".
But I'm not checked all peripherals. Can conf...
06/20/2014
- I am having some trouble with a data acquisition system.
Using MDK_2012-08-10
There are two tasks (among others) that perform the data acquisition. The data is streaming in from the mcBSP and is loaded into a common buffer by the ... - JC 02:12 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Andrey, Can you share your linux 3.14 port. What did you have to change to get it working? Are you using device tree?
Thanks Jonathan - Hello,ALL
I want to test the DspFpgaSpi, but not successfully setup,Could anyone give me some instructions?
Before I have successfully tested the GPIO from your help, Thank you very much!
This the VHDL code Setup
//////////////////... - MW 08:45 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using custom DTS in yocto flow
- Right now, the kernel recipe that gets used for our dev kit is indeed in the meta-mitysom-5csx/recipes-kernel/linux folder.
You will need to get familiar with "bitbake":http://www.yoctoproject.org/docs/1.6/bitbake-user-manual/bitbak...
06/19/2014
- GG 09:13 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello,
Your CORE_GPIO_MODULE and base address (0x66000080) do not match one another. The address should be the CORE offset times 0x80 bytes + 0x66000000.
So - LY 02:26 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the VHDL code for gpio setup
/----------------------------------------------------------------------------/
--Gpio setup... - GG 01:09 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello,
- LY 03:27 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Help me check out the gpio Setup,It is not work.
- Thank you very much,Mike
- MW 03:11 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Help me check out the gpio Setup,It is not work.
- The address for the constructor is not correct. The Address is: the CORE offset times 0x80 bytes + 0x66000000.
In your example, it should be 4*0x80 = 0x66000200.
The code looks OK, though you only need a 0x1 instead of a 0x3 for w... - Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the VHDL code for gpio setup
/----------------------------------------------------------------------------/
--Gpio setup... - AM 08:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Mike, thank you for fast response.
In Linux 3.14 (from Yocto Project) this leads to disabling cpufreq because it cant locate CVDD regulator.
How you think can I simply change constraints? This doesn't broke my MityDSP?
- MW 08:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- In the hardware, the TPS65023 used for the MityDSP-L138 has the following voltages that are defaulted using the hardware strapping pins:
VDCDC1 -> 1.2 V (core)
VDCDC2 -> 1.8 V (mDDR, DVDD18, DVDD3318_C, FPGA bank voltages)
VDCDC3 -... - Hello,
I use MityDSP-L138F and Linux kernel from git://support.criticallink.com/home/git/linux-davinci.git but want upgrade to 3.14. I found inconsistent config of TPS65023 in board-mityomapl138.c. This file describe tps65023_regulato...
06/18/2014
- Posting on behalf of a customer and for future reference as well:
How do you get yocto to use a custom dts instead of the socfpga_mitysom5csx_devkit.dts?
The customer will be checking the kernel source and dts into version control ... - JC 12:57 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- When I enabled the dma I got the following errors when i plugged in the flash drive.
- JC 11:07 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- I was able to scp a 12 MB file without any errors
- JC 11:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Also you can buy the cables prebuilt.
USB mini 5 pin to USB A Female
http://www.amazon.com/USB-Female-Mini-Male-Adapter/sim/B0016RNX2I/2 - JC 10:41 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- How were you experiencing the unstable ethernet? Just transferring a file?
- HK 10:36 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- That changed stuff a bit. I now get more messages and the usb-msd driver seems to wake up.
But during initialization, i get error messages of disconnect and reconnect - see the attached log. I'm not sure whether the problem's in the c... - BD 10:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hannes, please let us know if this resolves your issue. We actually fixed this same problem on our MitySOM-335x module a few days before you posted your question.
For the sake of those searching the forum in the future, the MitySOM-3... - JC 09:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Got it working.
- HK 09:11 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- I don't think so. Udev primarily loads the driver and gets called once the driver does something. In the boot log you can see that the usb enumeration hangs during kernel initialization (usb is compiled in) and before init (and therefor ...
- MW 09:03 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Wondering if this is perhaps a udev issue?
- HK 08:58 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Exactly. But the mass storage driver itself gets loaded and then stalls (no /dev/sd* gets created).
- JC 08:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- Ok I was able to get things to the point where it will atleast detect the insertion of the flash drive by changing the usb register from MUSB_OTG to MUSB_HOST. I suspect that this is where you are at.
- HK 01:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB2.0 Host on MityDSP-L138F
- I tried changing between PIO and DMA before. That changed nothing about the problem - It enumerates the device and then stops.
Another thing:
If I plug in an external USB hub, the Linux detects that. Afterwards if i plug anything in,...