Activity
From 10/07/2023 to 11/05/2023
11/03/2023
- JC 04:15 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Boot issue, I2C0 (PCB Dev Post)
- Jonathan,
Apologies on the delay, we've had most of the systems tied up in-use for the past few weeks but I was able to grab some UART captures this morning.
I've attached 4 files - BOOT1-4. BOOT1 did not boot successfully...seems ...
11/02/2023
- DR 02:35 AM MitySOM-5CSX Altera Cyclone V PCB Development: RE: MSEL[4] and return current cap...
- Sorry if I wasn't clear. The caps are optional. They might help in a worst case situation, but for most designs they are overkill. Leaving one off won't be a problem. If you are doing a design and have the option to put them on, it w...
11/01/2023
- AF 11:34 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: MSEL[4] and return current cap...
- Hi David,
I understand that, but the eval board only has them on MSEL[3:0] and does not have one on MSEL[4]. So, should there be one on MSEL[4] on any design using the MitySOM or not?
Thanks,
Austin - DR 07:38 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: MSEL[4] and return current cap...
- The intention of the caps to ground on these signals is to allow some high frequency ground currents from the SOM I/O's going off-SOM to have additional paths to ground, since the MSEL signals (and other listed signals) are essentially D...
10/28/2023
- The dev board has MSEL[3:0] with 1000pF caps, and MSEL[4] does not have a cap, unless I missed it. In the design guide:
7.4 Return Currents
The module’s edge connector has GND connections distributed along the interface pinout to ma...
10/27/2023
- DV 06:10 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Link missing on System Design Overview wiki page
- Thank you for bringing this to our attention, I've updated the text on that wiki page so it now links to our reference project.
Dan
10/26/2023
- SA 08:00 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to boot FPGA from U-Boot without having the uboot.env file in my SD card
- Hi everyone,
For anyone who is reading, I have figured it out and I hope this will help you.
The U-Boot is running a script, see the bootcmd below - AK 10:57 AM MitySOM-AM57X Software Development: RE: Error in Cloning the branches of MitySOM
- It was an issue with TI's git server which got solved now.. The above discussion can be ignored.. thank you
- Following the procedure in the link: https://support.criticallink.com/redmine/projects/mitysom_am57x/wiki/Linux_Kernel_Yocto_for_MitySOM-AM57X, I have used the docker images for cloning the MitySOM branches to the oe-layersetup folder in...
- (posted on behalf of a customer)
on this URL:
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview
it says:
"Create a new project or start from the Critical Link MityARM-5CSX reference pro...
10/25/2023
- AF 06:54 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Standoff on Mounting Hole Locations page
- Part number 91115A501 is a 3/8" size standoff (1/8" tall, 4-40, hex). The one on the deb board I have is 1/4" size, which is part number 91115A160.
https://www.mcmaster.com/catalog/129/3674/91115A160
10/23/2023
- JC 02:06 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Boot issue, I2C0 (PCB Dev Post)
- Any updates?
10/20/2023
- SA 10:38 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to boot FPGA from U-Boot without having the uboot.env file in my SD card
- Hello,
I was wondering, I found in u-boot-socfpga/include/configs - Hello,
As a follow up from this question:https://support.criticallink.com/redmine/boards/45/topics/6501
Luckily, I was able to compile U-Boot 2019 from your CriticalLink repo and compile the Linux kernal and Yocto Rootfs as specifi...