Mity CPU Platforms

07/13/2026

01:13 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Good morning,
I have readded the PCIe RP IP, but it I still can't regenerate/update the a5e because the tool complai... Eleonora Haralanova

07/10/2026

08:15 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A: Getting the Splash Screen to Appear Earlier

Okay good to hear. Jonathan Cormier

08:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A: Getting the Splash Screen to Appear Earlier

The changes work great, got it working with our display no problem!
I see what you mean with the scrambled splashs... Holden Wozniak

04:06 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=shortlog;h=refs/heads/2025.01-am62a-hdmi-splash
Here ar... Jonathan Cormier

03:55 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

I believe the PCIe RP IP needs to be regenerated / re-added if you switch between production silicon or R0 silicon so... Mike Fiorenza

03:36 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Yes,
The actual label on the SOM is A5ED-B64-144-SRC-X, but the box says A5ED-B64-144-SRI-X
I checked the SBC also... Eleonora Haralanova

02:57 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Eleonora,
Can you read the label / sticker that is on the SOM module? I believe the device you actually have insta... Mike Fiorenza

01:46 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

It actually came back with different FPGA - the one that you have
jtagconfig
1) USB-BlasterII [USB-1]
4BA06477... Eleonora Haralanova

07/09/2026

09:21 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

No the SD card is irrelevant at this stage. JTAG talks directly to the SoC device.
Have you confirmed the device y... Mike Fiorenza

09:15 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

I get the correct device
quartus_pfg -i output_files/a5e.hps.jic | grep "Device"
Device name: A5ED065BB32A
Devic... Eleonora Haralanova

08:39 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Correction to my last statement, jtagconfig doesn't list the temperature / speed grade (because it is not a gating fa... Mike Fiorenza

08:34 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Hi Eleonora,
Yes *A5ED065BB32AI4S* is the correct part number for *A5ED-B64-144-SRI* .
Please confirm the outpu... Mike Fiorenza

08:18 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Hello Mike,
Deleting the u-boot-socfpga and bootloade.stamp and running make jic did give me test/ folder and produc... Eleonora Haralanova

08:01 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

I have made some good progress on this today. I've got to do some cleanup but i'll try to push a test branch for you... Jonathan Cormier

01:27 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

Note one thing I ran into is the ti-dss driver in 2025 u-boot, doesn't currently support switching to video port 1 (w... Jonathan Cormier

12:54 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

I am also attaching the Linux dts, I know the bindings are a little different for the u-boot drivers so I tried to ma... Holden Wozniak

07/08/2026

09:52 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic

Hi Eleonora,
The test/Kconfig error most likely means the U-Boot source tree under software/bootloader/u-boot-socf... Mike Fiorenza

07:08 PM MitySOM-A5 FPGA Development: Not being able to Make jic

Hi,
I have the example design for PCIE Rootport. It was in a special folder for my use. I made some changes and I'm... Eleonora Haralanova

07:50 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

Can you share the changes you've made so far as a patch/diff? Jonathan Cormier

06:57 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

I was able to create nodes in the u-boot device tree for my panel, pwm-backlight, and the video driver (dss).
In d... Holden Wozniak

07/07/2026

01:32 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

Our som.c is mostly a copy of their evm.c
https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=blob;f=board/... Jonathan Cormier

01:07 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

Just for some clarification, the documentation says to modify board/ti/am62ax/evm.c to change the SPL init function a... Holden Wozniak

07/06/2026

03:44 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

If you run into any roadblocks, let me know. We can schedule a working meeting if needed. Jonathan Cormier

03:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

Holden Wozniak wrote in message#7361:
> Sounds good. Getting an early image on the display is one of the last big th... Jonathan Cormier

03:28 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

Sounds good. Getting an early image on the display is one of the last big things I need to do to get our device in a ... Holden Wozniak

03:13 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier

There was some change I think around TI's SDK 9, that greatly delayed the /dev/fb0 creation. I didn't dig into it at... Jonathan Cormier

02:44 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: AM62A: Getting the Splash Screen to Appear Earlier

Good morning,
I am finding that the psplash screen comes up very late while the kernel is initializing to the poin... Holden Wozniak

06/26/2026

09:33 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using GPIO command on UBoot command line...is there any pin mapping between HPS pin # and GPIO pin #?

From Dan at CL (Thanks Dan!)
Our reference project has the following HPS IO set as GPIO:
- GPIO40 — edge pin 264 ... Austin Franklin

06/25/2026

09:31 PM MitySOM-5CSX Altera Cyclone V Software Development: Using GPIO command on UBoot command line...is there any pin mapping between HPS pin # and GPIO pin #?

Hi,
I have the CriticalLink UBoot image on a terminal program. There is the GPIO set/clear/toggle command. It wa... Austin Franklin

06/24/2026

03:38 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: LED on nCONFIG...

Hi Mike,
Thank you for the confirmation. I've attached a picture of my proposed update to our MitySOM boards. An... Austin Franklin

02:21 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: LED on nCONFIG...

Hi Austin,
You are correct that the Cyclone V cannot drive this pin. It is a configuration control input which mus... Mike Fiorenza

06/23/2026

10:46 PM MitySOM-5CSX Altera Cyclone V PCB Development: LED on nCONFIG...

On the CriticalLink MitySOM-5CSX development board, there is an LED D100 connected to nCONFIG (pin 39). According to... Austin Franklin