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1
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/*
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2
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* Driver for OMAP-UART controller.
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3
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* Based on drivers/serial/8250.c
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4
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*
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5
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* Copyright (C) 2010 Texas Instruments.
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6
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*
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7
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* Authors:
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8
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* Govindraj R <govindraj.raja@ti.com>
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9
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* Thara Gopinath <thara@ti.com>
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10
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*
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11
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* This program is free software; you can redistribute it and/or modify
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12
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* it under the terms of the GNU General Public License as published by
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13
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* the Free Software Foundation; either version 2 of the License, or
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14
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* (at your option) any later version.
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15
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*
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16
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* Note: This driver is made separate from 8250 driver as we cannot
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17
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* over load 8250 driver with omap platform specific configuration for
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18
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* features like DMA, it makes easier to implement features like DMA and
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19
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* hardware flow control and software flow control configuration with
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20
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* this driver as required for the omap-platform.
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21
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*/
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22
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23
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#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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24
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#define SUPPORT_SYSRQ
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25
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#endif
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26
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27
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#include <linux/module.h>
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28
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#include <linux/init.h>
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29
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#include <linux/console.h>
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30
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#include <linux/serial_reg.h>
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31
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#include <linux/delay.h>
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32
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#include <linux/slab.h>
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33
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#include <linux/tty.h>
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34
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#include <linux/tty_flip.h>
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35
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#include <linux/io.h>
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36
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#include <linux/dma-mapping.h>
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37
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#include <linux/clk.h>
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38
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#include <linux/serial_core.h>
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39
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#include <linux/irq.h>
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40
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#include <linux/gpio.h>
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41
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#include <linux/uaccess.h>
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42
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#include <linux/pm_runtime.h>
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43
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#include <linux/of.h>
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44
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45
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#include <plat/dma.h>
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46
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#include <plat/dmtimer.h>
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47
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#include <plat/omap-serial.h>
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48
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49
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#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
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50
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51
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static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
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52
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53
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/* Forward declaration of functions */
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54
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static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
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55
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static void serial_omap_rxdma_poll(unsigned long uart_no);
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56
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static int serial_omap_start_rxdma(struct uart_omap_port *up);
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57
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static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
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58
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59
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static struct workqueue_struct *serial_omap_uart_wq;
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60
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61
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static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
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62
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{
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63
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offset <<= up->port.regshift;
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64
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return readw(up->port.membase + offset);
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65
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}
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66
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67
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static inline void serial_out(struct uart_omap_port *up, int offset, int value)
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68
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{
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69
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offset <<= up->port.regshift;
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70
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writew(value, up->port.membase + offset);
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71
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}
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72
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73
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static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
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74
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{
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75
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serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
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76
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serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
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77
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UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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78
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serial_out(up, UART_FCR, 0);
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79
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}
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80
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81
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/*
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82
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* serial_omap_get_divisor - calculate divisor value
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83
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* @port: uart port info
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84
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* @baud: baudrate for which divisor needs to be calculated.
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85
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*
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86
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* We have written our own function to get the divisor so as to support
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87
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* 13x mode. 3Mbps Baudrate as an different divisor.
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88
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* Reference OMAP TRM Chapter 17:
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89
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* Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
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90
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* referring to oversampling - divisor value
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91
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* baudrate 460,800 to 3,686,400 all have divisor 13
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92
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* except 3,000,000 which has divisor value 16
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93
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*/
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94
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static unsigned int
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95
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serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
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96
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{
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97
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unsigned int divisor;
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98
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99
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if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
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100
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divisor = 13;
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101
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else
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102
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divisor = 16;
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103
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return port->uartclk/(baud * divisor);
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104
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}
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105
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106
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static void serial_omap_stop_rxdma(struct uart_omap_port *up)
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107
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{
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108
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if (up->uart_dma.rx_dma_used) {
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109
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del_timer(&up->uart_dma.rx_timer);
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110
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omap_stop_dma(up->uart_dma.rx_dma_channel);
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111
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omap_free_dma(up->uart_dma.rx_dma_channel);
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112
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up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
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113
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up->uart_dma.rx_dma_used = false;
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114
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pm_runtime_mark_last_busy(&up->pdev->dev);
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115
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pm_runtime_put_autosuspend(&up->pdev->dev);
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116
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}
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117
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}
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118
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119
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static void serial_omap_enable_ms(struct uart_port *port)
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120
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{
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121
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struct uart_omap_port *up = (struct uart_omap_port *)port;
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122
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123
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dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
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124
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125
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pm_runtime_get_sync(&up->pdev->dev);
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126
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up->ier |= UART_IER_MSI;
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127
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serial_out(up, UART_IER, up->ier);
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128
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pm_runtime_put(&up->pdev->dev);
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129
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}
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130
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131
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static inline void wait_for_xmitr(struct uart_omap_port *up);
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132
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133
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static void serial_omap_stop_tx(struct uart_port *port)
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134
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{
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135
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struct uart_omap_port *up = (struct uart_omap_port *)port;
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136
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137
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if (up->use_dma &&
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138
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up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
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139
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/*
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140
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* Check if dma is still active. If yes do nothing,
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141
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* return. Else stop dma
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142
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*/
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143
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if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
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144
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return;
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145
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omap_stop_dma(up->uart_dma.tx_dma_channel);
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146
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omap_free_dma(up->uart_dma.tx_dma_channel);
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147
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up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
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148
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pm_runtime_mark_last_busy(&up->pdev->dev);
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149
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pm_runtime_put_autosuspend(&up->pdev->dev);
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150
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}
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151
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152
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pm_runtime_get_sync(&up->pdev->dev);
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153
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if (up->ier & UART_IER_THRI) {
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154
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up->ier &= ~UART_IER_THRI;
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155
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serial_out(up, UART_IER, up->ier);
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156
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}
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157
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158
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pm_runtime_mark_last_busy(&up->pdev->dev);
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159
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pm_runtime_put_autosuspend(&up->pdev->dev);
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160
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}
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161
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162
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static void serial_omap_stop_rx(struct uart_port *port)
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163
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{
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164
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struct uart_omap_port *up = (struct uart_omap_port *)port;
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165
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166
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pm_runtime_get_sync(&up->pdev->dev);
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167
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if (up->use_dma)
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168
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serial_omap_stop_rxdma(up);
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169
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up->ier &= ~UART_IER_RLSI;
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170
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up->port.read_status_mask &= ~UART_LSR_DR;
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171
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serial_out(up, UART_IER, up->ier);
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172
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pm_runtime_mark_last_busy(&up->pdev->dev);
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173
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pm_runtime_put_autosuspend(&up->pdev->dev);
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174
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}
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175
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176
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static inline void receive_chars(struct uart_omap_port *up,
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177
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unsigned int *status)
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178
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{
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179
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struct tty_struct *tty = up->port.state->port.tty;
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180
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unsigned int flag, lsr = *status;
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181
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unsigned char ch = 0;
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182
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int max_count = 256;
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183
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184
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do {
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185
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if (likely(lsr & UART_LSR_DR))
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186
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ch = serial_in(up, UART_RX);
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187
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flag = TTY_NORMAL;
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188
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up->port.icount.rx++;
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189
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|
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190
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if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
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191
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/*
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192
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* For statistics only
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193
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*/
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194
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if (lsr & UART_LSR_BI) {
|
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195
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lsr &= ~(UART_LSR_FE | UART_LSR_PE);
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196
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up->port.icount.brk++;
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197
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/*
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198
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* We do the SysRQ and SAK checking
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199
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* here because otherwise the break
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200
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* may get masked by ignore_status_mask
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201
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* or read_status_mask.
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202
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*/
|
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203
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if (uart_handle_break(&up->port))
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204
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goto ignore_char;
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205
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} else if (lsr & UART_LSR_PE) {
|
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206
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up->port.icount.parity++;
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207
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} else if (lsr & UART_LSR_FE) {
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208
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up->port.icount.frame++;
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209
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}
|
|
210
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|
|
211
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if (lsr & UART_LSR_OE)
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212
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up->port.icount.overrun++;
|
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213
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|
|
214
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/*
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|
215
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* Mask off conditions which should be ignored.
|
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216
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*/
|
|
217
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lsr &= up->port.read_status_mask;
|
|
218
|
|
|
219
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#ifdef CONFIG_SERIAL_OMAP_CONSOLE
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|
220
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if (up->port.line == up->port.cons->index) {
|
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221
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/* Recover the break flag from console xmit */
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222
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lsr |= up->lsr_break_flag;
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|
223
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}
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|
224
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#endif
|
|
225
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if (lsr & UART_LSR_BI)
|
|
226
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flag = TTY_BREAK;
|
|
227
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else if (lsr & UART_LSR_PE)
|
|
228
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flag = TTY_PARITY;
|
|
229
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else if (lsr & UART_LSR_FE)
|
|
230
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flag = TTY_FRAME;
|
|
231
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}
|
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232
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|
|
233
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if (uart_handle_sysrq_char(&up->port, ch))
|
|
234
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goto ignore_char;
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235
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uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
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|
236
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ignore_char:
|
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237
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lsr = serial_in(up, UART_LSR);
|
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238
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} while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
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239
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spin_unlock(&up->port.lock);
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|
240
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tty_flip_buffer_push(tty);
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241
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spin_lock(&up->port.lock);
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242
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}
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|
243
|
|
|
244
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static void transmit_chars(struct uart_omap_port *up)
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|
245
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{
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|
246
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struct circ_buf *xmit = &up->port.state->xmit;
|
|
247
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int count;
|
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248
|
|
|
249
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if (up->port.x_char) {
|
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250
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serial_out(up, UART_TX, up->port.x_char);
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251
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up->port.icount.tx++;
|
|
252
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up->port.x_char = 0;
|
|
253
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return;
|
|
254
|
}
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|
255
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if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
|
|
256
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serial_omap_stop_tx(&up->port);
|
|
257
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return;
|
|
258
|
}
|
|
259
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count = up->port.fifosize / 4;
|
|
260
|
do {
|
|
261
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serial_out(up, UART_TX, xmit->buf[xmit->tail]);
|
|
262
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
|
|
263
|
up->port.icount.tx++;
|
|
264
|
if (uart_circ_empty(xmit))
|
|
265
|
break;
|
|
266
|
} while (--count > 0);
|
|
267
|
|
|
268
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
|
269
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uart_write_wakeup(&up->port);
|
|
270
|
|
|
271
|
if (uart_circ_empty(xmit))
|
|
272
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serial_omap_stop_tx(&up->port);
|
|
273
|
}
|
|
274
|
|
|
275
|
static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
|
|
276
|
{
|
|
277
|
int val;
|
|
278
|
if (!(up->ier & UART_IER_THRI)) {
|
|
279
|
up->ier |= UART_IER_THRI;
|
|
280
|
serial_out(up, UART_IER, up->ier);
|
|
281
|
}
|
|
282
|
|
|
283
|
wait_for_xmitr(up);
|
|
284
|
if (up->rs485.flags & SER_RS485_ENABLED) {
|
|
285
|
/* Disable RS485 TX EN */
|
|
286
|
val = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
|
|
287
|
gpio_set_value(up->rs485.gpio_pin, val);
|
|
288
|
printk("omap_enable_ier_thri:SETGPIO(%d)\n",val);
|
|
289
|
}
|
|
290
|
}
|
|
291
|
|
|
292
|
static void serial_omap_start_tx(struct uart_port *port)
|
|
293
|
{
|
|
294
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
295
|
struct circ_buf *xmit;
|
|
296
|
unsigned int start;
|
|
297
|
int ret = 0;
|
|
298
|
int val;
|
|
299
|
|
|
300
|
if (up->rs485.flags & SER_RS485_ENABLED) {
|
|
301
|
/* Enable RS485 TX EN */
|
|
302
|
val = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 0 : 1;
|
|
303
|
gpio_set_value(up->rs485.gpio_pin, val);
|
|
304
|
printk("omap_start_tx:SETGPIO(%d)\n",val);
|
|
305
|
}
|
|
306
|
|
|
307
|
if (!up->use_dma) {
|
|
308
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
309
|
serial_omap_enable_ier_thri(up);
|
|
310
|
pm_runtime_mark_last_busy(&up->pdev->dev);
|
|
311
|
pm_runtime_put_autosuspend(&up->pdev->dev);
|
|
312
|
return;
|
|
313
|
}
|
|
314
|
|
|
315
|
if (up->uart_dma.tx_dma_used)
|
|
316
|
return;
|
|
317
|
|
|
318
|
xmit = &up->port.state->xmit;
|
|
319
|
|
|
320
|
if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
|
|
321
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
322
|
ret = omap_request_dma(up->uart_dma.uart_dma_tx,
|
|
323
|
"UART Tx DMA",
|
|
324
|
(void *)uart_tx_dma_callback, up,
|
|
325
|
&(up->uart_dma.tx_dma_channel));
|
|
326
|
|
|
327
|
if (ret < 0) {
|
|
328
|
serial_omap_enable_ier_thri(up);
|
|
329
|
return;
|
|
330
|
}
|
|
331
|
}
|
|
332
|
spin_lock(&(up->uart_dma.tx_lock));
|
|
333
|
up->uart_dma.tx_dma_used = true;
|
|
334
|
spin_unlock(&(up->uart_dma.tx_lock));
|
|
335
|
|
|
336
|
start = up->uart_dma.tx_buf_dma_phys +
|
|
337
|
(xmit->tail & (UART_XMIT_SIZE - 1));
|
|
338
|
|
|
339
|
up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
|
|
340
|
/*
|
|
341
|
* It is a circular buffer. See if the buffer has wounded back.
|
|
342
|
* If yes it will have to be transferred in two separate dma
|
|
343
|
* transfers
|
|
344
|
*/
|
|
345
|
if (start + up->uart_dma.tx_buf_size >=
|
|
346
|
up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
|
|
347
|
up->uart_dma.tx_buf_size =
|
|
348
|
(up->uart_dma.tx_buf_dma_phys +
|
|
349
|
UART_XMIT_SIZE) - start;
|
|
350
|
|
|
351
|
omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
|
|
352
|
OMAP_DMA_AMODE_CONSTANT,
|
|
353
|
up->uart_dma.uart_base, 0, 0);
|
|
354
|
omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
|
|
355
|
OMAP_DMA_AMODE_POST_INC, start, 0, 0);
|
|
356
|
omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
|
|
357
|
OMAP_DMA_DATA_TYPE_S8,
|
|
358
|
up->uart_dma.tx_buf_size, 1,
|
|
359
|
OMAP_DMA_SYNC_ELEMENT,
|
|
360
|
up->uart_dma.uart_dma_tx, 0);
|
|
361
|
/* FIXME: Cache maintenance needed here? */
|
|
362
|
omap_start_dma(up->uart_dma.tx_dma_channel);
|
|
363
|
}
|
|
364
|
|
|
365
|
static unsigned int check_modem_status(struct uart_omap_port *up)
|
|
366
|
{
|
|
367
|
unsigned int status;
|
|
368
|
|
|
369
|
status = serial_in(up, UART_MSR);
|
|
370
|
status |= up->msr_saved_flags;
|
|
371
|
up->msr_saved_flags = 0;
|
|
372
|
if ((status & UART_MSR_ANY_DELTA) == 0)
|
|
373
|
return status;
|
|
374
|
|
|
375
|
if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
|
|
376
|
up->port.state != NULL) {
|
|
377
|
if (status & UART_MSR_TERI)
|
|
378
|
up->port.icount.rng++;
|
|
379
|
if (status & UART_MSR_DDSR)
|
|
380
|
up->port.icount.dsr++;
|
|
381
|
if (status & UART_MSR_DDCD)
|
|
382
|
uart_handle_dcd_change
|
|
383
|
(&up->port, status & UART_MSR_DCD);
|
|
384
|
if (status & UART_MSR_DCTS)
|
|
385
|
uart_handle_cts_change
|
|
386
|
(&up->port, status & UART_MSR_CTS);
|
|
387
|
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
|
|
388
|
}
|
|
389
|
|
|
390
|
return status;
|
|
391
|
}
|
|
392
|
|
|
393
|
/**
|
|
394
|
* serial_omap_irq() - This handles the interrupt from one port
|
|
395
|
* @irq: uart port irq number
|
|
396
|
* @dev_id: uart port info
|
|
397
|
*/
|
|
398
|
static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
|
|
399
|
{
|
|
400
|
struct uart_omap_port *up = dev_id;
|
|
401
|
unsigned int iir, lsr;
|
|
402
|
unsigned long flags;
|
|
403
|
|
|
404
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
405
|
iir = serial_in(up, UART_IIR);
|
|
406
|
if (iir & UART_IIR_NO_INT) {
|
|
407
|
pm_runtime_mark_last_busy(&up->pdev->dev);
|
|
408
|
pm_runtime_put_autosuspend(&up->pdev->dev);
|
|
409
|
return IRQ_NONE;
|
|
410
|
}
|
|
411
|
|
|
412
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
413
|
lsr = serial_in(up, UART_LSR);
|
|
414
|
if (iir & UART_IIR_RLSI) {
|
|
415
|
if (!up->use_dma) {
|
|
416
|
if (lsr & UART_LSR_DR)
|
|
417
|
receive_chars(up, &lsr);
|
|
418
|
} else {
|
|
419
|
up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
|
|
420
|
serial_out(up, UART_IER, up->ier);
|
|
421
|
if ((serial_omap_start_rxdma(up) != 0) &&
|
|
422
|
(lsr & UART_LSR_DR))
|
|
423
|
receive_chars(up, &lsr);
|
|
424
|
}
|
|
425
|
}
|
|
426
|
|
|
427
|
check_modem_status(up);
|
|
428
|
if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
|
|
429
|
transmit_chars(up);
|
|
430
|
|
|
431
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
432
|
pm_runtime_mark_last_busy(&up->pdev->dev);
|
|
433
|
pm_runtime_put_autosuspend(&up->pdev->dev);
|
|
434
|
|
|
435
|
up->port_activity = jiffies;
|
|
436
|
return IRQ_HANDLED;
|
|
437
|
}
|
|
438
|
|
|
439
|
static unsigned int serial_omap_tx_empty(struct uart_port *port)
|
|
440
|
{
|
|
441
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
442
|
unsigned long flags = 0;
|
|
443
|
unsigned int ret = 0;
|
|
444
|
|
|
445
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
446
|
dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
|
|
447
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
448
|
ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
|
|
449
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
450
|
pm_runtime_put(&up->pdev->dev);
|
|
451
|
return ret;
|
|
452
|
}
|
|
453
|
|
|
454
|
static unsigned int serial_omap_get_mctrl(struct uart_port *port)
|
|
455
|
{
|
|
456
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
457
|
unsigned char status;
|
|
458
|
unsigned int ret = 0;
|
|
459
|
|
|
460
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
461
|
status = check_modem_status(up);
|
|
462
|
pm_runtime_put(&up->pdev->dev);
|
|
463
|
|
|
464
|
dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
|
|
465
|
|
|
466
|
if (status & UART_MSR_DCD)
|
|
467
|
ret |= TIOCM_CAR;
|
|
468
|
if (status & UART_MSR_RI)
|
|
469
|
ret |= TIOCM_RNG;
|
|
470
|
if (status & UART_MSR_DSR)
|
|
471
|
ret |= TIOCM_DSR;
|
|
472
|
if (status & UART_MSR_CTS)
|
|
473
|
ret |= TIOCM_CTS;
|
|
474
|
return ret;
|
|
475
|
}
|
|
476
|
|
|
477
|
static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|
478
|
{
|
|
479
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
480
|
unsigned char mcr = 0;
|
|
481
|
|
|
482
|
dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
|
|
483
|
if (mctrl & TIOCM_RTS)
|
|
484
|
mcr |= UART_MCR_RTS;
|
|
485
|
if (mctrl & TIOCM_DTR)
|
|
486
|
mcr |= UART_MCR_DTR;
|
|
487
|
if (mctrl & TIOCM_OUT1)
|
|
488
|
mcr |= UART_MCR_OUT1;
|
|
489
|
if (mctrl & TIOCM_OUT2)
|
|
490
|
mcr |= UART_MCR_OUT2;
|
|
491
|
if (mctrl & TIOCM_LOOP)
|
|
492
|
mcr |= UART_MCR_LOOP;
|
|
493
|
|
|
494
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
495
|
up->mcr = serial_in(up, UART_MCR);
|
|
496
|
up->mcr |= mcr;
|
|
497
|
serial_out(up, UART_MCR, up->mcr);
|
|
498
|
pm_runtime_put(&up->pdev->dev);
|
|
499
|
}
|
|
500
|
|
|
501
|
static void serial_omap_break_ctl(struct uart_port *port, int break_state)
|
|
502
|
{
|
|
503
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
504
|
unsigned long flags = 0;
|
|
505
|
|
|
506
|
dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
|
|
507
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
508
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
509
|
if (break_state == -1)
|
|
510
|
up->lcr |= UART_LCR_SBC;
|
|
511
|
else
|
|
512
|
up->lcr &= ~UART_LCR_SBC;
|
|
513
|
serial_out(up, UART_LCR, up->lcr);
|
|
514
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
515
|
pm_runtime_put(&up->pdev->dev);
|
|
516
|
}
|
|
517
|
|
|
518
|
static int serial_omap_startup(struct uart_port *port)
|
|
519
|
{
|
|
520
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
521
|
unsigned long flags = 0;
|
|
522
|
int retval;
|
|
523
|
|
|
524
|
/*
|
|
525
|
* Allocate the IRQ
|
|
526
|
*/
|
|
527
|
retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
|
|
528
|
up->name, up);
|
|
529
|
if (retval)
|
|
530
|
return retval;
|
|
531
|
|
|
532
|
dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
|
|
533
|
|
|
534
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
535
|
/*
|
|
536
|
* Clear the FIFO buffers and disable them.
|
|
537
|
* (they will be reenabled in set_termios())
|
|
538
|
*/
|
|
539
|
serial_omap_clear_fifos(up);
|
|
540
|
/* For Hardware flow control */
|
|
541
|
serial_out(up, UART_MCR, UART_MCR_RTS);
|
|
542
|
|
|
543
|
/*
|
|
544
|
* Clear the interrupt registers.
|
|
545
|
*/
|
|
546
|
(void) serial_in(up, UART_LSR);
|
|
547
|
if (serial_in(up, UART_LSR) & UART_LSR_DR)
|
|
548
|
(void) serial_in(up, UART_RX);
|
|
549
|
(void) serial_in(up, UART_IIR);
|
|
550
|
(void) serial_in(up, UART_MSR);
|
|
551
|
|
|
552
|
/*
|
|
553
|
* Now, initialize the UART
|
|
554
|
*/
|
|
555
|
serial_out(up, UART_LCR, UART_LCR_WLEN8);
|
|
556
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
557
|
/*
|
|
558
|
* Most PC uarts need OUT2 raised to enable interrupts.
|
|
559
|
*/
|
|
560
|
up->port.mctrl |= TIOCM_OUT2;
|
|
561
|
serial_omap_set_mctrl(&up->port, up->port.mctrl);
|
|
562
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
563
|
|
|
564
|
up->msr_saved_flags = 0;
|
|
565
|
if (up->use_dma) {
|
|
566
|
free_page((unsigned long)up->port.state->xmit.buf);
|
|
567
|
up->port.state->xmit.buf = dma_alloc_coherent(NULL,
|
|
568
|
UART_XMIT_SIZE,
|
|
569
|
(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
|
|
570
|
0);
|
|
571
|
init_timer(&(up->uart_dma.rx_timer));
|
|
572
|
up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
|
|
573
|
up->uart_dma.rx_timer.data = up->port.line;
|
|
574
|
/* Currently the buffer size is 4KB. Can increase it */
|
|
575
|
up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
|
|
576
|
up->uart_dma.rx_buf_size,
|
|
577
|
(dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
|
|
578
|
}
|
|
579
|
/*
|
|
580
|
* Finally, enable interrupts. Note: Modem status interrupts
|
|
581
|
* are set via set_termios(), which will be occurring imminently
|
|
582
|
* anyway, so we don't enable them here.
|
|
583
|
*/
|
|
584
|
up->ier = UART_IER_RLSI | UART_IER_RDI;
|
|
585
|
serial_out(up, UART_IER, up->ier);
|
|
586
|
|
|
587
|
/* Enable module level wake up */
|
|
588
|
serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
|
|
589
|
|
|
590
|
pm_runtime_mark_last_busy(&up->pdev->dev);
|
|
591
|
pm_runtime_put_autosuspend(&up->pdev->dev);
|
|
592
|
up->port_activity = jiffies;
|
|
593
|
return 0;
|
|
594
|
}
|
|
595
|
|
|
596
|
static void serial_omap_shutdown(struct uart_port *port)
|
|
597
|
{
|
|
598
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
599
|
unsigned long flags = 0;
|
|
600
|
int val;
|
|
601
|
|
|
602
|
dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
|
|
603
|
|
|
604
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
605
|
/*
|
|
606
|
* Disable interrupts from this port
|
|
607
|
*/
|
|
608
|
up->ier = 0;
|
|
609
|
serial_out(up, UART_IER, 0);
|
|
610
|
|
|
611
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
612
|
up->port.mctrl &= ~TIOCM_OUT2;
|
|
613
|
serial_omap_set_mctrl(&up->port, up->port.mctrl);
|
|
614
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
615
|
|
|
616
|
/*
|
|
617
|
* Disable break condition and FIFOs
|
|
618
|
*/
|
|
619
|
serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
|
|
620
|
serial_omap_clear_fifos(up);
|
|
621
|
|
|
622
|
/* if in RS485 mode, make sure we disable the driver */
|
|
623
|
if (up->rs485.flags & SER_RS485_ENABLED) {
|
|
624
|
val = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
|
|
625
|
gpio_set_value(up->rs485.gpio_pin, val);
|
|
626
|
}
|
|
627
|
|
|
628
|
/*
|
|
629
|
* Read data port to reset things, and then free the irq
|
|
630
|
*/
|
|
631
|
if (serial_in(up, UART_LSR) & UART_LSR_DR)
|
|
632
|
(void) serial_in(up, UART_RX);
|
|
633
|
if (up->use_dma) {
|
|
634
|
dma_free_coherent(up->port.dev,
|
|
635
|
UART_XMIT_SIZE, up->port.state->xmit.buf,
|
|
636
|
up->uart_dma.tx_buf_dma_phys);
|
|
637
|
up->port.state->xmit.buf = NULL;
|
|
638
|
serial_omap_stop_rx(port);
|
|
639
|
dma_free_coherent(up->port.dev,
|
|
640
|
up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
|
|
641
|
up->uart_dma.rx_buf_dma_phys);
|
|
642
|
up->uart_dma.rx_buf = NULL;
|
|
643
|
}
|
|
644
|
|
|
645
|
pm_runtime_put(&up->pdev->dev);
|
|
646
|
free_irq(up->port.irq, up);
|
|
647
|
}
|
|
648
|
|
|
649
|
static inline void
|
|
650
|
serial_omap_configure_xonxoff
|
|
651
|
(struct uart_omap_port *up, struct ktermios *termios)
|
|
652
|
{
|
|
653
|
up->lcr = serial_in(up, UART_LCR);
|
|
654
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
655
|
up->efr = serial_in(up, UART_EFR);
|
|
656
|
serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
|
|
657
|
|
|
658
|
serial_out(up, UART_XON1, termios->c_cc[VSTART]);
|
|
659
|
serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
|
|
660
|
|
|
661
|
/* clear SW control mode bits */
|
|
662
|
up->efr &= OMAP_UART_SW_CLR;
|
|
663
|
|
|
664
|
/*
|
|
665
|
* IXON Flag:
|
|
666
|
* Enable XON/XOFF flow control on output.
|
|
667
|
* Transmit XON1, XOFF1
|
|
668
|
*/
|
|
669
|
if (termios->c_iflag & IXON)
|
|
670
|
up->efr |= OMAP_UART_SW_TX;
|
|
671
|
|
|
672
|
/*
|
|
673
|
* IXOFF Flag:
|
|
674
|
* Enable XON/XOFF flow control on input.
|
|
675
|
* Receiver compares XON1, XOFF1.
|
|
676
|
*/
|
|
677
|
if (termios->c_iflag & IXOFF)
|
|
678
|
up->efr |= OMAP_UART_SW_RX;
|
|
679
|
|
|
680
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
681
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
682
|
|
|
683
|
up->mcr = serial_in(up, UART_MCR);
|
|
684
|
|
|
685
|
/*
|
|
686
|
* IXANY Flag:
|
|
687
|
* Enable any character to restart output.
|
|
688
|
* Operation resumes after receiving any
|
|
689
|
* character after recognition of the XOFF character
|
|
690
|
*/
|
|
691
|
if (termios->c_iflag & IXANY)
|
|
692
|
up->mcr |= UART_MCR_XONANY;
|
|
693
|
|
|
694
|
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
|
|
695
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
696
|
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
|
|
697
|
/* Enable special char function UARTi.EFR_REG[5] and
|
|
698
|
* load the new software flow control mode IXON or IXOFF
|
|
699
|
* and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
|
|
700
|
*/
|
|
701
|
serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
|
|
702
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
703
|
|
|
704
|
serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
|
|
705
|
serial_out(up, UART_LCR, up->lcr);
|
|
706
|
}
|
|
707
|
|
|
708
|
static void serial_omap_uart_qos_work(struct work_struct *work)
|
|
709
|
{
|
|
710
|
struct uart_omap_port *up = container_of(work, struct uart_omap_port,
|
|
711
|
qos_work);
|
|
712
|
|
|
713
|
pm_qos_update_request(&up->pm_qos_request, up->latency);
|
|
714
|
}
|
|
715
|
|
|
716
|
static void
|
|
717
|
serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
|
|
718
|
struct ktermios *old)
|
|
719
|
{
|
|
720
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
721
|
unsigned char cval = 0;
|
|
722
|
unsigned char efr = 0;
|
|
723
|
unsigned long flags = 0;
|
|
724
|
unsigned int baud, quot;
|
|
725
|
|
|
726
|
switch (termios->c_cflag & CSIZE) {
|
|
727
|
case CS5:
|
|
728
|
cval = UART_LCR_WLEN5;
|
|
729
|
break;
|
|
730
|
case CS6:
|
|
731
|
cval = UART_LCR_WLEN6;
|
|
732
|
break;
|
|
733
|
case CS7:
|
|
734
|
cval = UART_LCR_WLEN7;
|
|
735
|
break;
|
|
736
|
default:
|
|
737
|
case CS8:
|
|
738
|
cval = UART_LCR_WLEN8;
|
|
739
|
break;
|
|
740
|
}
|
|
741
|
|
|
742
|
if (termios->c_cflag & CSTOPB)
|
|
743
|
cval |= UART_LCR_STOP;
|
|
744
|
if (termios->c_cflag & PARENB)
|
|
745
|
cval |= UART_LCR_PARITY;
|
|
746
|
if (!(termios->c_cflag & PARODD))
|
|
747
|
cval |= UART_LCR_EPAR;
|
|
748
|
|
|
749
|
/*
|
|
750
|
* Ask the core to calculate the divisor for us.
|
|
751
|
*/
|
|
752
|
|
|
753
|
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
|
|
754
|
quot = serial_omap_get_divisor(port, baud);
|
|
755
|
|
|
756
|
/* calculate wakeup latency constraint */
|
|
757
|
up->calc_latency = (1000000 * up->port.fifosize) /
|
|
758
|
(1000 * baud / 8);
|
|
759
|
up->latency = up->calc_latency;
|
|
760
|
schedule_work(&up->qos_work);
|
|
761
|
|
|
762
|
up->dll = quot & 0xff;
|
|
763
|
up->dlh = quot >> 8;
|
|
764
|
up->mdr1 = UART_OMAP_MDR1_DISABLE;
|
|
765
|
|
|
766
|
up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
|
|
767
|
UART_FCR_ENABLE_FIFO;
|
|
768
|
if (up->use_dma)
|
|
769
|
up->fcr |= UART_FCR_DMA_SELECT;
|
|
770
|
|
|
771
|
/*
|
|
772
|
* Ok, we're now changing the port state. Do it with
|
|
773
|
* interrupts disabled.
|
|
774
|
*/
|
|
775
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
776
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
777
|
|
|
778
|
/*
|
|
779
|
* Update the per-port timeout.
|
|
780
|
*/
|
|
781
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
782
|
|
|
783
|
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
|
|
784
|
if (termios->c_iflag & INPCK)
|
|
785
|
up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
|
|
786
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
787
|
up->port.read_status_mask |= UART_LSR_BI;
|
|
788
|
|
|
789
|
/*
|
|
790
|
* Characters to ignore
|
|
791
|
*/
|
|
792
|
up->port.ignore_status_mask = 0;
|
|
793
|
if (termios->c_iflag & IGNPAR)
|
|
794
|
up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
|
|
795
|
if (termios->c_iflag & IGNBRK) {
|
|
796
|
up->port.ignore_status_mask |= UART_LSR_BI;
|
|
797
|
/*
|
|
798
|
* If we're ignoring parity and break indicators,
|
|
799
|
* ignore overruns too (for real raw support).
|
|
800
|
*/
|
|
801
|
if (termios->c_iflag & IGNPAR)
|
|
802
|
up->port.ignore_status_mask |= UART_LSR_OE;
|
|
803
|
}
|
|
804
|
|
|
805
|
/*
|
|
806
|
* ignore all characters if CREAD is not set
|
|
807
|
*/
|
|
808
|
if ((termios->c_cflag & CREAD) == 0)
|
|
809
|
up->port.ignore_status_mask |= UART_LSR_DR;
|
|
810
|
|
|
811
|
/*
|
|
812
|
* Modem status interrupts
|
|
813
|
*/
|
|
814
|
up->ier &= ~UART_IER_MSI;
|
|
815
|
if (UART_ENABLE_MS(&up->port, termios->c_cflag))
|
|
816
|
up->ier |= UART_IER_MSI;
|
|
817
|
serial_out(up, UART_IER, up->ier);
|
|
818
|
serial_out(up, UART_LCR, cval); /* reset DLAB */
|
|
819
|
up->lcr = cval;
|
|
820
|
up->scr = OMAP_UART_SCR_TX_EMPTY;
|
|
821
|
|
|
822
|
/* FIFOs and DMA Settings */
|
|
823
|
|
|
824
|
/* FCR can be changed only when the
|
|
825
|
* baud clock is not running
|
|
826
|
* DLL_REG and DLH_REG set to 0.
|
|
827
|
*/
|
|
828
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
829
|
serial_out(up, UART_DLL, 0);
|
|
830
|
serial_out(up, UART_DLM, 0);
|
|
831
|
serial_out(up, UART_LCR, 0);
|
|
832
|
|
|
833
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
834
|
|
|
835
|
up->efr = serial_in(up, UART_EFR);
|
|
836
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
837
|
|
|
838
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
839
|
up->mcr = serial_in(up, UART_MCR);
|
|
840
|
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
|
|
841
|
/* FIFO ENABLE, DMA MODE */
|
|
842
|
serial_out(up, UART_FCR, up->fcr);
|
|
843
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
844
|
|
|
845
|
if (up->use_dma) {
|
|
846
|
serial_out(up, UART_TI752_TLR, 0);
|
|
847
|
up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
|
|
848
|
}
|
|
849
|
|
|
850
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
|
851
|
|
|
852
|
serial_out(up, UART_EFR, up->efr);
|
|
853
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
854
|
serial_out(up, UART_MCR, up->mcr);
|
|
855
|
|
|
856
|
/* Protocol, Baud Rate, and Interrupt Settings */
|
|
857
|
|
|
858
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
859
|
serial_omap_mdr1_errataset(up, up->mdr1);
|
|
860
|
else
|
|
861
|
serial_out(up, UART_OMAP_MDR1, up->mdr1);
|
|
862
|
|
|
863
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
864
|
|
|
865
|
up->efr = serial_in(up, UART_EFR);
|
|
866
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
867
|
|
|
868
|
serial_out(up, UART_LCR, 0);
|
|
869
|
serial_out(up, UART_IER, 0);
|
|
870
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
871
|
|
|
872
|
serial_out(up, UART_DLL, up->dll); /* LS of divisor */
|
|
873
|
serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
|
|
874
|
|
|
875
|
serial_out(up, UART_LCR, 0);
|
|
876
|
serial_out(up, UART_IER, up->ier);
|
|
877
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
878
|
|
|
879
|
serial_out(up, UART_EFR, up->efr);
|
|
880
|
serial_out(up, UART_LCR, cval);
|
|
881
|
|
|
882
|
if (baud > 230400 && baud != 3000000)
|
|
883
|
up->mdr1 = UART_OMAP_MDR1_13X_MODE;
|
|
884
|
else
|
|
885
|
up->mdr1 = UART_OMAP_MDR1_16X_MODE;
|
|
886
|
|
|
887
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
888
|
serial_omap_mdr1_errataset(up, up->mdr1);
|
|
889
|
else
|
|
890
|
serial_out(up, UART_OMAP_MDR1, up->mdr1);
|
|
891
|
|
|
892
|
/* Hardware Flow Control Configuration */
|
|
893
|
|
|
894
|
if (termios->c_cflag & CRTSCTS) {
|
|
895
|
efr |= (UART_EFR_CTS | UART_EFR_RTS);
|
|
896
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
897
|
|
|
898
|
up->mcr = serial_in(up, UART_MCR);
|
|
899
|
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
|
|
900
|
|
|
901
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
902
|
up->efr = serial_in(up, UART_EFR);
|
|
903
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
904
|
|
|
905
|
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
|
|
906
|
serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
|
|
907
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
908
|
serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
|
|
909
|
serial_out(up, UART_LCR, cval);
|
|
910
|
}
|
|
911
|
|
|
912
|
serial_omap_set_mctrl(&up->port, up->port.mctrl);
|
|
913
|
/* Software Flow Control Configuration */
|
|
914
|
serial_omap_configure_xonxoff(up, termios);
|
|
915
|
|
|
916
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
917
|
pm_runtime_put(&up->pdev->dev);
|
|
918
|
dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
|
|
919
|
}
|
|
920
|
|
|
921
|
static void
|
|
922
|
serial_omap_pm(struct uart_port *port, unsigned int state,
|
|
923
|
unsigned int oldstate)
|
|
924
|
{
|
|
925
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
926
|
unsigned char efr;
|
|
927
|
|
|
928
|
dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
|
|
929
|
|
|
930
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
931
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
932
|
efr = serial_in(up, UART_EFR);
|
|
933
|
serial_out(up, UART_EFR, efr | UART_EFR_ECB);
|
|
934
|
serial_out(up, UART_LCR, 0);
|
|
935
|
|
|
936
|
serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
|
|
937
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
938
|
serial_out(up, UART_EFR, efr);
|
|
939
|
serial_out(up, UART_LCR, 0);
|
|
940
|
|
|
941
|
if (!device_may_wakeup(&up->pdev->dev)) {
|
|
942
|
if (!state)
|
|
943
|
pm_runtime_forbid(&up->pdev->dev);
|
|
944
|
else
|
|
945
|
pm_runtime_allow(&up->pdev->dev);
|
|
946
|
}
|
|
947
|
|
|
948
|
pm_runtime_put(&up->pdev->dev);
|
|
949
|
}
|
|
950
|
|
|
951
|
static void serial_omap_release_port(struct uart_port *port)
|
|
952
|
{
|
|
953
|
dev_dbg(port->dev, "serial_omap_release_port+\n");
|
|
954
|
}
|
|
955
|
|
|
956
|
static int serial_omap_request_port(struct uart_port *port)
|
|
957
|
{
|
|
958
|
dev_dbg(port->dev, "serial_omap_request_port+\n");
|
|
959
|
return 0;
|
|
960
|
}
|
|
961
|
|
|
962
|
static void serial_omap_config_port(struct uart_port *port, int flags)
|
|
963
|
{
|
|
964
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
965
|
|
|
966
|
dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
|
|
967
|
up->port.line);
|
|
968
|
up->port.type = PORT_OMAP;
|
|
969
|
}
|
|
970
|
|
|
971
|
static int
|
|
972
|
serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
973
|
{
|
|
974
|
/* we don't want the core code to modify any port params */
|
|
975
|
dev_dbg(port->dev, "serial_omap_verify_port+\n");
|
|
976
|
return -EINVAL;
|
|
977
|
}
|
|
978
|
|
|
979
|
static const char *
|
|
980
|
serial_omap_type(struct uart_port *port)
|
|
981
|
{
|
|
982
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
983
|
|
|
984
|
dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
|
|
985
|
return up->name;
|
|
986
|
}
|
|
987
|
|
|
988
|
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
|
|
989
|
|
|
990
|
static inline void wait_for_xmitr(struct uart_omap_port *up)
|
|
991
|
{
|
|
992
|
unsigned int status, tmout = 10000;
|
|
993
|
|
|
994
|
/* Wait up to 10ms for the character(s) to be sent. */
|
|
995
|
do {
|
|
996
|
status = serial_in(up, UART_LSR);
|
|
997
|
|
|
998
|
if (status & UART_LSR_BI)
|
|
999
|
up->lsr_break_flag = UART_LSR_BI;
|
|
1000
|
|
|
1001
|
if (--tmout == 0)
|
|
1002
|
break;
|
|
1003
|
udelay(1);
|
|
1004
|
} while ((status & BOTH_EMPTY) != BOTH_EMPTY);
|
|
1005
|
|
|
1006
|
/* Wait up to 1s for flow control if necessary */
|
|
1007
|
if (up->port.flags & UPF_CONS_FLOW) {
|
|
1008
|
tmout = 1000000;
|
|
1009
|
for (tmout = 1000000; tmout; tmout--) {
|
|
1010
|
unsigned int msr = serial_in(up, UART_MSR);
|
|
1011
|
|
|
1012
|
up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
|
|
1013
|
if (msr & UART_MSR_CTS)
|
|
1014
|
break;
|
|
1015
|
|
|
1016
|
udelay(1);
|
|
1017
|
}
|
|
1018
|
}
|
|
1019
|
}
|
|
1020
|
|
|
1021
|
#ifdef CONFIG_CONSOLE_POLL
|
|
1022
|
|
|
1023
|
static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
|
|
1024
|
{
|
|
1025
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
1026
|
|
|
1027
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
1028
|
wait_for_xmitr(up);
|
|
1029
|
serial_out(up, UART_TX, ch);
|
|
1030
|
pm_runtime_put(&up->pdev->dev);
|
|
1031
|
}
|
|
1032
|
|
|
1033
|
static int serial_omap_poll_get_char(struct uart_port *port)
|
|
1034
|
{
|
|
1035
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
1036
|
unsigned int status;
|
|
1037
|
|
|
1038
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
1039
|
status = serial_in(up, UART_LSR);
|
|
1040
|
if (!(status & UART_LSR_DR))
|
|
1041
|
return NO_POLL_CHAR;
|
|
1042
|
|
|
1043
|
status = serial_in(up, UART_RX);
|
|
1044
|
pm_runtime_put(&up->pdev->dev);
|
|
1045
|
return status;
|
|
1046
|
}
|
|
1047
|
|
|
1048
|
#endif /* CONFIG_CONSOLE_POLL */
|
|
1049
|
|
|
1050
|
#ifdef CONFIG_SERIAL_OMAP_CONSOLE
|
|
1051
|
|
|
1052
|
static struct uart_omap_port *serial_omap_console_ports[4];
|
|
1053
|
|
|
1054
|
static struct uart_driver serial_omap_reg;
|
|
1055
|
|
|
1056
|
static void serial_omap_console_putchar(struct uart_port *port, int ch)
|
|
1057
|
{
|
|
1058
|
struct uart_omap_port *up = (struct uart_omap_port *)port;
|
|
1059
|
|
|
1060
|
wait_for_xmitr(up);
|
|
1061
|
serial_out(up, UART_TX, ch);
|
|
1062
|
}
|
|
1063
|
|
|
1064
|
static void
|
|
1065
|
serial_omap_console_write(struct console *co, const char *s,
|
|
1066
|
unsigned int count)
|
|
1067
|
{
|
|
1068
|
struct uart_omap_port *up = serial_omap_console_ports[co->index];
|
|
1069
|
unsigned long flags;
|
|
1070
|
unsigned int ier;
|
|
1071
|
int locked = 1;
|
|
1072
|
|
|
1073
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
1074
|
|
|
1075
|
local_irq_save(flags);
|
|
1076
|
if (up->port.sysrq)
|
|
1077
|
locked = 0;
|
|
1078
|
else if (oops_in_progress)
|
|
1079
|
locked = spin_trylock(&up->port.lock);
|
|
1080
|
else
|
|
1081
|
spin_lock(&up->port.lock);
|
|
1082
|
|
|
1083
|
/*
|
|
1084
|
* First save the IER then disable the interrupts
|
|
1085
|
*/
|
|
1086
|
ier = serial_in(up, UART_IER);
|
|
1087
|
serial_out(up, UART_IER, 0);
|
|
1088
|
|
|
1089
|
uart_console_write(&up->port, s, count, serial_omap_console_putchar);
|
|
1090
|
|
|
1091
|
/*
|
|
1092
|
* Finally, wait for transmitter to become empty
|
|
1093
|
* and restore the IER
|
|
1094
|
*/
|
|
1095
|
wait_for_xmitr(up);
|
|
1096
|
serial_out(up, UART_IER, ier);
|
|
1097
|
/*
|
|
1098
|
* The receive handling will happen properly because the
|
|
1099
|
* receive ready bit will still be set; it is not cleared
|
|
1100
|
* on read. However, modem control will not, we must
|
|
1101
|
* call it if we have saved something in the saved flags
|
|
1102
|
* while processing with interrupts off.
|
|
1103
|
*/
|
|
1104
|
if (up->msr_saved_flags)
|
|
1105
|
check_modem_status(up);
|
|
1106
|
|
|
1107
|
pm_runtime_mark_last_busy(&up->pdev->dev);
|
|
1108
|
pm_runtime_put_autosuspend(&up->pdev->dev);
|
|
1109
|
if (locked)
|
|
1110
|
spin_unlock(&up->port.lock);
|
|
1111
|
local_irq_restore(flags);
|
|
1112
|
}
|
|
1113
|
|
|
1114
|
static int __init
|
|
1115
|
serial_omap_console_setup(struct console *co, char *options)
|
|
1116
|
{
|
|
1117
|
struct uart_omap_port *up;
|
|
1118
|
int baud = 115200;
|
|
1119
|
int bits = 8;
|
|
1120
|
int parity = 'n';
|
|
1121
|
int flow = 'n';
|
|
1122
|
|
|
1123
|
if (serial_omap_console_ports[co->index] == NULL)
|
|
1124
|
return -ENODEV;
|
|
1125
|
up = serial_omap_console_ports[co->index];
|
|
1126
|
|
|
1127
|
if (options)
|
|
1128
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
1129
|
|
|
1130
|
return uart_set_options(&up->port, co, baud, parity, bits, flow);
|
|
1131
|
}
|
|
1132
|
|
|
1133
|
static struct console serial_omap_console = {
|
|
1134
|
.name = OMAP_SERIAL_NAME,
|
|
1135
|
.write = serial_omap_console_write,
|
|
1136
|
.device = uart_console_device,
|
|
1137
|
.setup = serial_omap_console_setup,
|
|
1138
|
.flags = CON_PRINTBUFFER,
|
|
1139
|
.index = -1,
|
|
1140
|
.data = &serial_omap_reg,
|
|
1141
|
};
|
|
1142
|
|
|
1143
|
static void serial_omap_add_console_port(struct uart_omap_port *up)
|
|
1144
|
{
|
|
1145
|
serial_omap_console_ports[up->port.line] = up;
|
|
1146
|
}
|
|
1147
|
|
|
1148
|
#define OMAP_CONSOLE (&serial_omap_console)
|
|
1149
|
|
|
1150
|
#else
|
|
1151
|
|
|
1152
|
#define OMAP_CONSOLE NULL
|
|
1153
|
|
|
1154
|
static inline void serial_omap_add_console_port(struct uart_omap_port *up)
|
|
1155
|
{}
|
|
1156
|
|
|
1157
|
#endif
|
|
1158
|
|
|
1159
|
static int
|
|
1160
|
serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
|
|
1161
|
{
|
|
1162
|
int r = 0;
|
|
1163
|
int val;
|
|
1164
|
struct uart_omap_port *p = (struct uart_omap_port *)port;
|
|
1165
|
|
|
1166
|
spin_lock(&port->lock);
|
|
1167
|
|
|
1168
|
/* TODO - disable transmitter ? */
|
|
1169
|
|
|
1170
|
if (rs485conf->flags & SER_RS485_ENABLED) {
|
|
1171
|
val = (p->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
|
|
1172
|
/* if using GPIO, request the resource and set it up */
|
|
1173
|
if (rs485conf->flags & SER_RS485_USE_GPIO) {
|
|
1174
|
/* get gpio resources if not already set */
|
|
1175
|
if (!(p->rs485.flags & SER_RS485_USE_GPIO) ||
|
|
1176
|
(p->rs485.gpio_pin != rs485conf->gpio_pin)) {
|
|
1177
|
printk("UART: %s;\t",p->name);
|
|
1178
|
printk("gpioNR: %d\n",rs485conf->gpio_pin);
|
|
1179
|
r = gpio_request(rs485conf->gpio_pin,
|
|
1180
|
"RS485 TXE");
|
|
1181
|
if (r) {
|
|
1182
|
dev_warn(port->dev,
|
|
1183
|
"Could not request GPIO %d : %d\n",
|
|
1184
|
rs485conf->gpio_pin, r);
|
|
1185
|
r = -EFAULT;
|
|
1186
|
goto exit_bail;
|
|
1187
|
|
|
1188
|
}
|
|
1189
|
|
|
1190
|
r = gpio_direction_output(rs485conf->gpio_pin, val);
|
|
1191
|
if (r) {
|
|
1192
|
dev_warn(port->dev,
|
|
1193
|
"Could not drive GPIO %d : %d\n",
|
|
1194
|
rs485conf->gpio_pin, r);
|
|
1195
|
r = -EFAULT;
|
|
1196
|
goto exit_bail;
|
|
1197
|
}
|
|
1198
|
|
|
1199
|
/* free up old pin */
|
|
1200
|
//TODO: What if old pin is same as current?!!?!?
|
|
1201
|
//if (p->rs485.flags & SER_RS485_USE_GPIO)
|
|
1202
|
//gpio_free(p->rs485.gpio_pin);
|
|
1203
|
}
|
|
1204
|
} else { /* RTS pin requested */
|
|
1205
|
dev_warn(port->dev, "Must use GPIO for RS485 Support\n");
|
|
1206
|
goto exit_bail;
|
|
1207
|
}
|
|
1208
|
}
|
|
1209
|
p->rs485 = *rs485conf;
|
|
1210
|
|
|
1211
|
exit_bail:
|
|
1212
|
spin_unlock(&port->lock);
|
|
1213
|
return r;
|
|
1214
|
|
|
1215
|
}
|
|
1216
|
|
|
1217
|
static int
|
|
1218
|
serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
|
|
1219
|
{
|
|
1220
|
struct serial_rs485 rs485conf;
|
|
1221
|
|
|
1222
|
switch (cmd) {
|
|
1223
|
case TIOCSRS485:
|
|
1224
|
if (copy_from_user(&rs485conf, (struct serial_rs485 *)arg,
|
|
1225
|
sizeof(rs485conf)))
|
|
1226
|
return -EFAULT;
|
|
1227
|
serial_omap_config_rs485(port, &rs485conf);
|
|
1228
|
break;
|
|
1229
|
|
|
1230
|
case TIOCGRS485:
|
|
1231
|
if (copy_to_user((struct serial_rs485 *)arg,
|
|
1232
|
&((struct uart_omap_port *)port)->rs485,
|
|
1233
|
sizeof(rs485conf)))
|
|
1234
|
return -EFAULT;
|
|
1235
|
break;
|
|
1236
|
|
|
1237
|
default:
|
|
1238
|
return -ENOIOCTLCMD;
|
|
1239
|
}
|
|
1240
|
|
|
1241
|
return 0;
|
|
1242
|
}
|
|
1243
|
|
|
1244
|
static struct uart_ops serial_omap_pops = {
|
|
1245
|
.tx_empty = serial_omap_tx_empty,
|
|
1246
|
.set_mctrl = serial_omap_set_mctrl,
|
|
1247
|
.get_mctrl = serial_omap_get_mctrl,
|
|
1248
|
.stop_tx = serial_omap_stop_tx,
|
|
1249
|
.start_tx = serial_omap_start_tx,
|
|
1250
|
.stop_rx = serial_omap_stop_rx,
|
|
1251
|
.enable_ms = serial_omap_enable_ms,
|
|
1252
|
.break_ctl = serial_omap_break_ctl,
|
|
1253
|
.startup = serial_omap_startup,
|
|
1254
|
.shutdown = serial_omap_shutdown,
|
|
1255
|
.set_termios = serial_omap_set_termios,
|
|
1256
|
.pm = serial_omap_pm,
|
|
1257
|
.type = serial_omap_type,
|
|
1258
|
.release_port = serial_omap_release_port,
|
|
1259
|
.request_port = serial_omap_request_port,
|
|
1260
|
.config_port = serial_omap_config_port,
|
|
1261
|
.verify_port = serial_omap_verify_port,
|
|
1262
|
.ioctl = serial_omap_ioctl,
|
|
1263
|
#ifdef CONFIG_CONSOLE_POLL
|
|
1264
|
.poll_put_char = serial_omap_poll_put_char,
|
|
1265
|
.poll_get_char = serial_omap_poll_get_char,
|
|
1266
|
#endif
|
|
1267
|
};
|
|
1268
|
|
|
1269
|
static struct uart_driver serial_omap_reg = {
|
|
1270
|
.owner = THIS_MODULE,
|
|
1271
|
.driver_name = "OMAP-SERIAL",
|
|
1272
|
.dev_name = OMAP_SERIAL_NAME,
|
|
1273
|
.nr = OMAP_MAX_HSUART_PORTS,
|
|
1274
|
.cons = OMAP_CONSOLE,
|
|
1275
|
};
|
|
1276
|
|
|
1277
|
#ifdef CONFIG_SUSPEND
|
|
1278
|
static int serial_omap_suspend(struct device *dev)
|
|
1279
|
{
|
|
1280
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
1281
|
|
|
1282
|
if (up) {
|
|
1283
|
uart_suspend_port(&serial_omap_reg, &up->port);
|
|
1284
|
flush_work_sync(&up->qos_work);
|
|
1285
|
}
|
|
1286
|
|
|
1287
|
return 0;
|
|
1288
|
}
|
|
1289
|
|
|
1290
|
static int serial_omap_resume(struct device *dev)
|
|
1291
|
{
|
|
1292
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
1293
|
|
|
1294
|
if (up)
|
|
1295
|
uart_resume_port(&serial_omap_reg, &up->port);
|
|
1296
|
return 0;
|
|
1297
|
}
|
|
1298
|
#endif
|
|
1299
|
|
|
1300
|
static void serial_omap_rxdma_poll(unsigned long uart_no)
|
|
1301
|
{
|
|
1302
|
struct uart_omap_port *up = ui[uart_no];
|
|
1303
|
unsigned int curr_dma_pos, curr_transmitted_size;
|
|
1304
|
int ret = 0;
|
|
1305
|
|
|
1306
|
curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
|
|
1307
|
if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
|
|
1308
|
(curr_dma_pos == 0)) {
|
|
1309
|
if (jiffies_to_msecs(jiffies - up->port_activity) <
|
|
1310
|
up->uart_dma.rx_timeout) {
|
|
1311
|
mod_timer(&up->uart_dma.rx_timer, jiffies +
|
|
1312
|
usecs_to_jiffies(up->uart_dma.rx_poll_rate));
|
|
1313
|
} else {
|
|
1314
|
serial_omap_stop_rxdma(up);
|
|
1315
|
up->ier |= (UART_IER_RDI | UART_IER_RLSI);
|
|
1316
|
serial_out(up, UART_IER, up->ier);
|
|
1317
|
}
|
|
1318
|
return;
|
|
1319
|
}
|
|
1320
|
|
|
1321
|
curr_transmitted_size = curr_dma_pos -
|
|
1322
|
up->uart_dma.prev_rx_dma_pos;
|
|
1323
|
up->port.icount.rx += curr_transmitted_size;
|
|
1324
|
tty_insert_flip_string(up->port.state->port.tty,
|
|
1325
|
up->uart_dma.rx_buf +
|
|
1326
|
(up->uart_dma.prev_rx_dma_pos -
|
|
1327
|
up->uart_dma.rx_buf_dma_phys),
|
|
1328
|
curr_transmitted_size);
|
|
1329
|
tty_flip_buffer_push(up->port.state->port.tty);
|
|
1330
|
up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
|
|
1331
|
if (up->uart_dma.rx_buf_size +
|
|
1332
|
up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
|
|
1333
|
ret = serial_omap_start_rxdma(up);
|
|
1334
|
if (ret < 0) {
|
|
1335
|
serial_omap_stop_rxdma(up);
|
|
1336
|
up->ier |= (UART_IER_RDI | UART_IER_RLSI);
|
|
1337
|
serial_out(up, UART_IER, up->ier);
|
|
1338
|
}
|
|
1339
|
} else {
|
|
1340
|
mod_timer(&up->uart_dma.rx_timer, jiffies +
|
|
1341
|
usecs_to_jiffies(up->uart_dma.rx_poll_rate));
|
|
1342
|
}
|
|
1343
|
up->port_activity = jiffies;
|
|
1344
|
}
|
|
1345
|
|
|
1346
|
static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
|
|
1347
|
{
|
|
1348
|
return;
|
|
1349
|
}
|
|
1350
|
|
|
1351
|
static int serial_omap_start_rxdma(struct uart_omap_port *up)
|
|
1352
|
{
|
|
1353
|
int ret = 0;
|
|
1354
|
|
|
1355
|
if (up->uart_dma.rx_dma_channel == -1) {
|
|
1356
|
pm_runtime_get_sync(&up->pdev->dev);
|
|
1357
|
ret = omap_request_dma(up->uart_dma.uart_dma_rx,
|
|
1358
|
"UART Rx DMA",
|
|
1359
|
(void *)uart_rx_dma_callback, up,
|
|
1360
|
&(up->uart_dma.rx_dma_channel));
|
|
1361
|
if (ret < 0)
|
|
1362
|
return ret;
|
|
1363
|
|
|
1364
|
omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
|
|
1365
|
OMAP_DMA_AMODE_CONSTANT,
|
|
1366
|
up->uart_dma.uart_base, 0, 0);
|
|
1367
|
omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
|
|
1368
|
OMAP_DMA_AMODE_POST_INC,
|
|
1369
|
up->uart_dma.rx_buf_dma_phys, 0, 0);
|
|
1370
|
omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
|
|
1371
|
OMAP_DMA_DATA_TYPE_S8,
|
|
1372
|
up->uart_dma.rx_buf_size, 1,
|
|
1373
|
OMAP_DMA_SYNC_ELEMENT,
|
|
1374
|
up->uart_dma.uart_dma_rx, 0);
|
|
1375
|
}
|
|
1376
|
up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
|
|
1377
|
/* FIXME: Cache maintenance needed here? */
|
|
1378
|
omap_start_dma(up->uart_dma.rx_dma_channel);
|
|
1379
|
mod_timer(&up->uart_dma.rx_timer, jiffies +
|
|
1380
|
usecs_to_jiffies(up->uart_dma.rx_poll_rate));
|
|
1381
|
up->uart_dma.rx_dma_used = true;
|
|
1382
|
return ret;
|
|
1383
|
}
|
|
1384
|
|
|
1385
|
static void serial_omap_continue_tx(struct uart_omap_port *up)
|
|
1386
|
{
|
|
1387
|
struct circ_buf *xmit = &up->port.state->xmit;
|
|
1388
|
unsigned int start = up->uart_dma.tx_buf_dma_phys
|
|
1389
|
+ (xmit->tail & (UART_XMIT_SIZE - 1));
|
|
1390
|
|
|
1391
|
if (uart_circ_empty(xmit))
|
|
1392
|
return;
|
|
1393
|
|
|
1394
|
up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
|
|
1395
|
/*
|
|
1396
|
* It is a circular buffer. See if the buffer has wounded back.
|
|
1397
|
* If yes it will have to be transferred in two separate dma
|
|
1398
|
* transfers
|
|
1399
|
*/
|
|
1400
|
if (start + up->uart_dma.tx_buf_size >=
|
|
1401
|
up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
|
|
1402
|
up->uart_dma.tx_buf_size =
|
|
1403
|
(up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
|
|
1404
|
omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
|
|
1405
|
OMAP_DMA_AMODE_CONSTANT,
|
|
1406
|
up->uart_dma.uart_base, 0, 0);
|
|
1407
|
omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
|
|
1408
|
OMAP_DMA_AMODE_POST_INC, start, 0, 0);
|
|
1409
|
omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
|
|
1410
|
OMAP_DMA_DATA_TYPE_S8,
|
|
1411
|
up->uart_dma.tx_buf_size, 1,
|
|
1412
|
OMAP_DMA_SYNC_ELEMENT,
|
|
1413
|
up->uart_dma.uart_dma_tx, 0);
|
|
1414
|
/* FIXME: Cache maintenance needed here? */
|
|
1415
|
omap_start_dma(up->uart_dma.tx_dma_channel);
|
|
1416
|
}
|
|
1417
|
|
|
1418
|
static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
|
|
1419
|
{
|
|
1420
|
struct uart_omap_port *up = (struct uart_omap_port *)data;
|
|
1421
|
struct circ_buf *xmit = &up->port.state->xmit;
|
|
1422
|
|
|
1423
|
xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
|
|
1424
|
(UART_XMIT_SIZE - 1);
|
|
1425
|
up->port.icount.tx += up->uart_dma.tx_buf_size;
|
|
1426
|
|
|
1427
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
|
1428
|
uart_write_wakeup(&up->port);
|
|
1429
|
|
|
1430
|
if (uart_circ_empty(xmit)) {
|
|
1431
|
spin_lock(&(up->uart_dma.tx_lock));
|
|
1432
|
serial_omap_stop_tx(&up->port);
|
|
1433
|
up->uart_dma.tx_dma_used = false;
|
|
1434
|
spin_unlock(&(up->uart_dma.tx_lock));
|
|
1435
|
} else {
|
|
1436
|
omap_stop_dma(up->uart_dma.tx_dma_channel);
|
|
1437
|
serial_omap_continue_tx(up);
|
|
1438
|
}
|
|
1439
|
up->port_activity = jiffies;
|
|
1440
|
return;
|
|
1441
|
}
|
|
1442
|
|
|
1443
|
static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
|
|
1444
|
{
|
|
1445
|
struct omap_uart_port_info *omap_up_info;
|
|
1446
|
|
|
1447
|
omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
|
|
1448
|
if (!omap_up_info)
|
|
1449
|
return NULL; /* out of memory */
|
|
1450
|
|
|
1451
|
of_property_read_u32(dev->of_node, "clock-frequency",
|
|
1452
|
&omap_up_info->uartclk);
|
|
1453
|
return omap_up_info;
|
|
1454
|
}
|
|
1455
|
|
|
1456
|
static int serial_omap_probe(struct platform_device *pdev)
|
|
1457
|
{
|
|
1458
|
struct uart_omap_port *up;
|
|
1459
|
struct resource *mem, *irq, *dma_tx, *dma_rx;
|
|
1460
|
struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
|
|
1461
|
int ret = -ENOSPC;
|
|
1462
|
|
|
1463
|
if (pdev->dev.of_node)
|
|
1464
|
omap_up_info = of_get_uart_port_info(&pdev->dev);
|
|
1465
|
|
|
1466
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
1467
|
if (!mem) {
|
|
1468
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
1469
|
return -ENODEV;
|
|
1470
|
}
|
|
1471
|
|
|
1472
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
1473
|
if (!irq) {
|
|
1474
|
dev_err(&pdev->dev, "no irq resource?\n");
|
|
1475
|
return -ENODEV;
|
|
1476
|
}
|
|
1477
|
|
|
1478
|
if (!request_mem_region(mem->start, resource_size(mem),
|
|
1479
|
pdev->dev.driver->name)) {
|
|
1480
|
dev_err(&pdev->dev, "memory region already claimed\n");
|
|
1481
|
return -EBUSY;
|
|
1482
|
}
|
|
1483
|
|
|
1484
|
dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
|
|
1485
|
if (!dma_rx) {
|
|
1486
|
ret = -EINVAL;
|
|
1487
|
goto err;
|
|
1488
|
}
|
|
1489
|
|
|
1490
|
dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
|
|
1491
|
if (!dma_tx) {
|
|
1492
|
ret = -EINVAL;
|
|
1493
|
goto err;
|
|
1494
|
}
|
|
1495
|
|
|
1496
|
up = kzalloc(sizeof(*up), GFP_KERNEL);
|
|
1497
|
if (up == NULL) {
|
|
1498
|
ret = -ENOMEM;
|
|
1499
|
goto do_release_region;
|
|
1500
|
}
|
|
1501
|
up->pdev = pdev;
|
|
1502
|
up->port.dev = &pdev->dev;
|
|
1503
|
up->port.type = PORT_OMAP;
|
|
1504
|
up->port.iotype = UPIO_MEM;
|
|
1505
|
up->port.irq = irq->start;
|
|
1506
|
|
|
1507
|
up->port.regshift = 2;
|
|
1508
|
up->port.fifosize = 64;
|
|
1509
|
up->port.ops = &serial_omap_pops;
|
|
1510
|
|
|
1511
|
if (pdev->dev.of_node)
|
|
1512
|
up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
|
|
1513
|
else
|
|
1514
|
up->port.line = pdev->id;
|
|
1515
|
|
|
1516
|
if (up->port.line < 0) {
|
|
1517
|
dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
|
|
1518
|
up->port.line);
|
|
1519
|
ret = -ENODEV;
|
|
1520
|
goto err;
|
|
1521
|
}
|
|
1522
|
|
|
1523
|
sprintf(up->name, "OMAP UART%d", up->port.line);
|
|
1524
|
up->port.mapbase = mem->start;
|
|
1525
|
up->port.membase = ioremap(mem->start, resource_size(mem));
|
|
1526
|
if (!up->port.membase) {
|
|
1527
|
dev_err(&pdev->dev, "can't ioremap UART\n");
|
|
1528
|
ret = -ENOMEM;
|
|
1529
|
goto err;
|
|
1530
|
}
|
|
1531
|
|
|
1532
|
up->port.flags = omap_up_info->flags;
|
|
1533
|
up->port.uartclk = omap_up_info->uartclk;
|
|
1534
|
if (!up->port.uartclk) {
|
|
1535
|
up->port.uartclk = DEFAULT_CLK_SPEED;
|
|
1536
|
dev_warn(&pdev->dev, "No clock speed specified: using default:"
|
|
1537
|
"%d\n", DEFAULT_CLK_SPEED);
|
|
1538
|
}
|
|
1539
|
up->uart_dma.uart_base = mem->start;
|
|
1540
|
up->errata = omap_up_info->errata;
|
|
1541
|
|
|
1542
|
if (omap_up_info->dma_enabled) {
|
|
1543
|
up->uart_dma.uart_dma_tx = dma_tx->start;
|
|
1544
|
up->uart_dma.uart_dma_rx = dma_rx->start;
|
|
1545
|
up->use_dma = 1;
|
|
1546
|
up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
|
|
1547
|
up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
|
|
1548
|
up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
|
|
1549
|
spin_lock_init(&(up->uart_dma.tx_lock));
|
|
1550
|
spin_lock_init(&(up->uart_dma.rx_lock));
|
|
1551
|
up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
|
|
1552
|
up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
|
|
1553
|
}
|
|
1554
|
|
|
1555
|
up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
|
|
1556
|
up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
|
|
1557
|
pm_qos_add_request(&up->pm_qos_request,
|
|
1558
|
PM_QOS_CPU_DMA_LATENCY, up->latency);
|
|
1559
|
serial_omap_uart_wq = create_singlethread_workqueue(up->name);
|
|
1560
|
INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
|
|
1561
|
|
|
1562
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
1563
|
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
|
1564
|
omap_up_info->autosuspend_timeout);
|
|
1565
|
|
|
1566
|
pm_runtime_irq_safe(&pdev->dev);
|
|
1567
|
pm_runtime_enable(&pdev->dev);
|
|
1568
|
pm_runtime_get_sync(&pdev->dev);
|
|
1569
|
|
|
1570
|
ui[up->port.line] = up;
|
|
1571
|
serial_omap_add_console_port(up);
|
|
1572
|
|
|
1573
|
ret = uart_add_one_port(&serial_omap_reg, &up->port);
|
|
1574
|
if (ret != 0)
|
|
1575
|
goto do_release_region;
|
|
1576
|
|
|
1577
|
pm_runtime_put(&pdev->dev);
|
|
1578
|
platform_set_drvdata(pdev, up);
|
|
1579
|
return 0;
|
|
1580
|
err:
|
|
1581
|
dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
|
|
1582
|
pdev->id, __func__, ret);
|
|
1583
|
do_release_region:
|
|
1584
|
release_mem_region(mem->start, resource_size(mem));
|
|
1585
|
return ret;
|
|
1586
|
}
|
|
1587
|
|
|
1588
|
static int serial_omap_remove(struct platform_device *dev)
|
|
1589
|
{
|
|
1590
|
struct uart_omap_port *up = platform_get_drvdata(dev);
|
|
1591
|
|
|
1592
|
if (up) {
|
|
1593
|
pm_runtime_disable(&up->pdev->dev);
|
|
1594
|
uart_remove_one_port(&serial_omap_reg, &up->port);
|
|
1595
|
pm_qos_remove_request(&up->pm_qos_request);
|
|
1596
|
|
|
1597
|
kfree(up);
|
|
1598
|
}
|
|
1599
|
|
|
1600
|
platform_set_drvdata(dev, NULL);
|
|
1601
|
return 0;
|
|
1602
|
}
|
|
1603
|
|
|
1604
|
/*
|
|
1605
|
* Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
|
|
1606
|
* The access to uart register after MDR1 Access
|
|
1607
|
* causes UART to corrupt data.
|
|
1608
|
*
|
|
1609
|
* Need a delay =
|
|
1610
|
* 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
|
|
1611
|
* give 10 times as much
|
|
1612
|
*/
|
|
1613
|
static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
|
|
1614
|
{
|
|
1615
|
u8 timeout = 255;
|
|
1616
|
|
|
1617
|
serial_out(up, UART_OMAP_MDR1, mdr1);
|
|
1618
|
udelay(2);
|
|
1619
|
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
|
|
1620
|
UART_FCR_CLEAR_RCVR);
|
|
1621
|
/*
|
|
1622
|
* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
|
|
1623
|
* TX_FIFO_E bit is 1.
|
|
1624
|
*/
|
|
1625
|
while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
|
|
1626
|
(UART_LSR_THRE | UART_LSR_DR))) {
|
|
1627
|
timeout--;
|
|
1628
|
if (!timeout) {
|
|
1629
|
/* Should *never* happen. we warn and carry on */
|
|
1630
|
dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
|
|
1631
|
serial_in(up, UART_LSR));
|
|
1632
|
break;
|
|
1633
|
}
|
|
1634
|
udelay(1);
|
|
1635
|
}
|
|
1636
|
}
|
|
1637
|
|
|
1638
|
static void serial_omap_restore_context(struct uart_omap_port *up)
|
|
1639
|
{
|
|
1640
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
1641
|
serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
|
|
1642
|
else
|
|
1643
|
serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
|
|
1644
|
|
|
1645
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
|
|
1646
|
serial_out(up, UART_EFR, UART_EFR_ECB);
|
|
1647
|
serial_out(up, UART_LCR, 0x0); /* Operational mode */
|
|
1648
|
serial_out(up, UART_IER, 0x0);
|
|
1649
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
|
|
1650
|
serial_out(up, UART_DLL, up->dll);
|
|
1651
|
serial_out(up, UART_DLM, up->dlh);
|
|
1652
|
serial_out(up, UART_LCR, 0x0); /* Operational mode */
|
|
1653
|
serial_out(up, UART_IER, up->ier);
|
|
1654
|
serial_out(up, UART_FCR, up->fcr);
|
|
1655
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
1656
|
serial_out(up, UART_MCR, up->mcr);
|
|
1657
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
|
|
1658
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
|
1659
|
serial_out(up, UART_EFR, up->efr);
|
|
1660
|
serial_out(up, UART_LCR, up->lcr);
|
|
1661
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
1662
|
serial_omap_mdr1_errataset(up, up->mdr1);
|
|
1663
|
else
|
|
1664
|
serial_out(up, UART_OMAP_MDR1, up->mdr1);
|
|
1665
|
}
|
|
1666
|
|
|
1667
|
#ifdef CONFIG_PM_RUNTIME
|
|
1668
|
static int serial_omap_runtime_suspend(struct device *dev)
|
|
1669
|
{
|
|
1670
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
1671
|
struct omap_uart_port_info *pdata = dev->platform_data;
|
|
1672
|
|
|
1673
|
if (!up)
|
|
1674
|
return -EINVAL;
|
|
1675
|
|
|
1676
|
if (!pdata || !pdata->enable_wakeup)
|
|
1677
|
return 0;
|
|
1678
|
|
|
1679
|
if (pdata->get_context_loss_count)
|
|
1680
|
up->context_loss_cnt = pdata->get_context_loss_count(dev);
|
|
1681
|
|
|
1682
|
if (device_may_wakeup(dev)) {
|
|
1683
|
if (!up->wakeups_enabled) {
|
|
1684
|
pdata->enable_wakeup(up->pdev, true);
|
|
1685
|
up->wakeups_enabled = true;
|
|
1686
|
}
|
|
1687
|
} else {
|
|
1688
|
if (up->wakeups_enabled) {
|
|
1689
|
pdata->enable_wakeup(up->pdev, false);
|
|
1690
|
up->wakeups_enabled = false;
|
|
1691
|
}
|
|
1692
|
}
|
|
1693
|
|
|
1694
|
/* Errata i291 */
|
|
1695
|
if (up->use_dma && pdata->set_forceidle &&
|
|
1696
|
(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
|
|
1697
|
pdata->set_forceidle(up->pdev);
|
|
1698
|
|
|
1699
|
up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
|
|
1700
|
schedule_work(&up->qos_work);
|
|
1701
|
|
|
1702
|
return 0;
|
|
1703
|
}
|
|
1704
|
|
|
1705
|
static int serial_omap_runtime_resume(struct device *dev)
|
|
1706
|
{
|
|
1707
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
1708
|
struct omap_uart_port_info *pdata = dev->platform_data;
|
|
1709
|
|
|
1710
|
if (up) {
|
|
1711
|
if (pdata->get_context_loss_count) {
|
|
1712
|
u32 loss_cnt = pdata->get_context_loss_count(dev);
|
|
1713
|
|
|
1714
|
if (up->context_loss_cnt != loss_cnt)
|
|
1715
|
serial_omap_restore_context(up);
|
|
1716
|
}
|
|
1717
|
|
|
1718
|
/* Errata i291 */
|
|
1719
|
if (up->use_dma && pdata->set_noidle &&
|
|
1720
|
(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
|
|
1721
|
pdata->set_noidle(up->pdev);
|
|
1722
|
|
|
1723
|
up->latency = up->calc_latency;
|
|
1724
|
schedule_work(&up->qos_work);
|
|
1725
|
}
|
|
1726
|
|
|
1727
|
return 0;
|
|
1728
|
}
|
|
1729
|
#endif
|
|
1730
|
|
|
1731
|
static const struct dev_pm_ops serial_omap_dev_pm_ops = {
|
|
1732
|
SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
|
|
1733
|
SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
|
|
1734
|
serial_omap_runtime_resume, NULL)
|
|
1735
|
};
|
|
1736
|
|
|
1737
|
#if defined(CONFIG_OF)
|
|
1738
|
static const struct of_device_id omap_serial_of_match[] = {
|
|
1739
|
{ .compatible = "ti,omap2-uart" },
|
|
1740
|
{ .compatible = "ti,omap3-uart" },
|
|
1741
|
{ .compatible = "ti,omap4-uart" },
|
|
1742
|
{},
|
|
1743
|
};
|
|
1744
|
MODULE_DEVICE_TABLE(of, omap_serial_of_match);
|
|
1745
|
#endif
|
|
1746
|
|
|
1747
|
static struct platform_driver serial_omap_driver = {
|
|
1748
|
.probe = serial_omap_probe,
|
|
1749
|
.remove = serial_omap_remove,
|
|
1750
|
.driver = {
|
|
1751
|
.name = DRIVER_NAME,
|
|
1752
|
.pm = &serial_omap_dev_pm_ops,
|
|
1753
|
.of_match_table = of_match_ptr(omap_serial_of_match),
|
|
1754
|
},
|
|
1755
|
};
|
|
1756
|
|
|
1757
|
static int __init serial_omap_init(void)
|
|
1758
|
{
|
|
1759
|
int ret;
|
|
1760
|
|
|
1761
|
ret = uart_register_driver(&serial_omap_reg);
|
|
1762
|
if (ret != 0)
|
|
1763
|
return ret;
|
|
1764
|
ret = platform_driver_register(&serial_omap_driver);
|
|
1765
|
if (ret != 0)
|
|
1766
|
uart_unregister_driver(&serial_omap_reg);
|
|
1767
|
return ret;
|
|
1768
|
}
|
|
1769
|
|
|
1770
|
static void __exit serial_omap_exit(void)
|
|
1771
|
{
|
|
1772
|
platform_driver_unregister(&serial_omap_driver);
|
|
1773
|
uart_unregister_driver(&serial_omap_reg);
|
|
1774
|
}
|
|
1775
|
|
|
1776
|
module_init(serial_omap_init);
|
|
1777
|
module_exit(serial_omap_exit);
|
|
1778
|
|
|
1779
|
MODULE_DESCRIPTION("OMAP High Speed UART driver");
|
|
1780
|
MODULE_LICENSE("GPL");
|
|
1781
|
MODULE_AUTHOR("Texas Instruments Inc");
|
