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RE: Ethernet RMII2 working in u-boot, but not kernel » 0001-Skyline-patch.patch

Jonathan Cormier, 10/29/2013 03:36 PM

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arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c
82 82 
 *
83 83 
 *****************************************************************************/
84 84 

  		




  
  85
  
    
static struct pinmux_config rmii2_pin_mux[] = {

  		




  
  86
  
    
   {"gpmc_csn3.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP},

  		




  
  87
  
    
//    {"gpmc_wait0.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP},

  		




  
  88
  
    
    {"gpmc_a0.rmii2_txen",  AM33XX_PIN_OUTPUT}, // --

  		




  
  89
  
    
    {"gpmc_a5.rmii2_txd0",   AM33XX_PIN_OUTPUT},  // --

  		




  
  90
  
    
    {"gpmc_a4.rmii2_txd1",   AM33XX_PIN_OUTPUT}, // ---

  		




  
  91
  
    
    {"gpmc_a11.rmii2_rxd0",  AM33XX_PIN_INPUT_PULLDOWN},  // --

  		




  
  92
  
    
    {"gpmc_a10.rmii2_rxd1",  AM33XX_PIN_INPUT_PULLDOWN}, // --

  		




  
  93
  
    
    {"mii1_col.rmii2_refclk",  AM33XX_PIN_INPUT_PULLDOWN},  // -- 

  		




  
  94
  
    
    {"mdio_data.mdio_data", AM33XX_PIN_INPUT_PULLUP},

  		




  
  95
  
    
    {"mdio_clk.mdio_clk",   AM33XX_PIN_OUTPUT_PULLUP},

  		




  
  96
  
    
    {NULL, 0}

  		




  
  97
  
    
};

  		




  85
  98
  
    
static struct pinmux_config rgmii2_pin_mux[] = {

  		




  86
  99
  
    
	{"gpmc_a0.rgmii2_tctl",	AM33XX_PIN_OUTPUT},

  		




  87
  100
  
    
	{"gpmc_a1.rgmii2_rctl",	AM33XX_PIN_INPUT_PULLDOWN},

  		




  ......




  101
  114
  
    
};

  		




  102
  115
  
    

  		




  103
  116
  
    
static struct pinmux_config lcdc_pin_mux[] = {

  		




  
  117
  
    
#if 0 //danm

  		




  104
  118
  
    
	{"lcd_data0.lcd_data0",		AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},

  		




  105
  119
  
    
	{"lcd_data1.lcd_data1",		AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},

  		




  106
  120
  
    
	{"lcd_data2.lcd_data2",		AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},

  		




  ......




  123
  137
  
    
	{"lcd_ac_bias_en.lcd_ac_bias_en", AM33XX_PIN_OUTPUT},

  		




  124
  138
  
    
	/* GPIO for the backlight */

  		




  125
  139
  
    
	{ "mcasp0_aclkx.gpio3_14", AM33XX_PIN_OUTPUT},

  		




  
  140
  
    
#endif

  		




  126
  141
  
    
	{NULL, 0}

  		




  127
  142
  
    
};

  		




  128
  143
  
    

  		




  ......




  133
  148
  
    
	{"mmc0_dat0.mmc0_dat0", AM33XX_PIN_INPUT_PULLUP},

  		




  134
  149
  
    
	{"mmc0_clk.mmc0_clk",   AM33XX_PIN_INPUT_PULLUP},

  		




  135
  150
  
    
	{"mmc0_cmd.mmc0_cmd",   AM33XX_PIN_INPUT_PULLUP},

  		




  136
  
  
    
	{"mii1_txen.gpio3_3",	AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */

  		




  137
  
  
    
	{"mii1_col.gpio3_0",	AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */

  		




  
  151
  
    
// danm   {"mii1_txen.gpio3_3",   AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */

  		




  
  152
  
    
//    {"mii1_col.gpio3_0",    AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */

  		




  138
  153
  
    
	{NULL, 0}

  		




  139
  154
  
    
};

  		




  140
  155
  
    

  		




  ......




  169
  184
  
    
};

  		




  170
  185
  
    

  		




  171
  186
  
    
static struct pinmux_config expansion_pin_mux[] = {

  		




  172
  
  
    
	{"uart0_ctsn.uart4_rxd", AM33XX_PIN_INPUT_PULLUP}, /* Exp0 RX */

  		




  173
  
  
    
	{"uart0_rtsn.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */

  		




  174
  
  
    
	{"mii1_rxd3.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, /* Exp1 RX */

  		




  175
  
  
    
	{"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* Exp1 TX */

  		




  176
  
  
    
	{"mii1_rxd1.gpio2_20", AM33XX_PULL_ENBL}, /* Exp1 TX EN */

  		




  177
  
  
    
	{"mii1_txclk.gpio3_9", AM33XX_PULL_ENBL}, /* Exp0 TX EN */

  		




  
  187
  
    
	{"uart1_rxd.uart1_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */

  		




  
  188
  
    
	{"uart1_txd.uart1_txd", AM33XX_PULL_ENBL},     /* Exp0 TX */

  		




  
  189
  
    
	{"mii1_rxd3.uart1_dtrn", AM33XX_PULL_ENBL},     /* uart 1 modem  */

  		




  
  190
  
    
	{"mii1_rxclk..uart1_dsrn", AM33XX_PULL_ENBL},     /* */

  		




  
  191
  
    
	{"mii1_txclk.uart1_dcdn", AM33XX_PULL_ENBL},     /* */

  		




  
  192
  
    

  		




  
  193
  
    
	{"spi0_sclk.uart2_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */

  		




  
  194
  
    
	{"spi0_d0.uart2_txd", AM33XX_PULL_ENBL},     /* Exp0 TX */

  		




  
  195
  
    

  		




  
  196
  
    
	{"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */

  		




  
  197
  
    
	{"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL},     /* - Exp0 TX */

  		




  
  198
  
    

  		




  
  199
  
    
	{"mii1_txd3.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* - Exp0 RX */

  		




  
  200
  
    
	{"mii1_txd2.uart4_txd", AM33XX_PULL_ENBL},     /* Exp0 TX */

  		




  
  201
  
    

  		




  
  202
  
    
	{"lcd_data9.uart5_rxd", AM33XX_PIN_INPUT_PULLUP},/*-  Exp0 RX */

  		




  
  203
  
    
	{"lcd_data8.uart5_txd", AM33XX_PULL_ENBL},     /*-  Exp0 TX */

  		




  178
  204
  
    
	{NULL, 0}

  		




  179
  205
  
    
};

  		




  180
  206
  
    

  		




  ......




  252
  278
  
    
	{

  		




  253
  279
  
    
		.mmc		= 1,

  		




  254
  280
  
    
		.caps		= MMC_CAP_4_BIT_DATA,

  		




  255
  
  
    
		.gpio_cd	= GPIO_TO_PIN(3, 3),

  		




  256
  
  
    
		.gpio_wp	= GPIO_TO_PIN(3, 0),

  		




  
  281
  
    
		.gpio_cd     = -EINVAL, // GPIO_TO_PIN(3, 3),

  		




  
  282
  
    
		.gpio_wp    = -EINVAL, //GPIO_TO_PIN(3, 0),

  		




  257
  283
  
    
		.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,

  		




  258
  284
  
    
	},

  		




  259
  285
  
    
	{

  		




  ......




  582
  608
  
    
static __init void baseboard_setup_enet(void)

  		




  583
  609
  
    
{

  		




  584
  610
  
    
	/* pinmux */

  		




  585
  
  
    
	setup_pin_mux(rgmii2_pin_mux);

  		




  
  611
  
    
	setup_pin_mux(rmii2_pin_mux);

  		




  586
  612
  
    

  		




  587
  613
  
    
	/* network configuration done in SOM code */

  		




  588
  614
  
    
	/* PHY address setup? */

  		












  

    
      arch/arm/mach-omap2/board-mityarm335x.c
    
  





  821
  821
  
    
	omap_serial_init();

  		




  822
  822
  
    
	am335x_rtc_init();

  		




  823
  823
  
    
	clkout2_enable();

  		




  824
  
  
    
	am33xx_cpsw_init(1); /* 1 == enable gigabit */

  		




  
  824
  
    
	am33xx_cpsw_init(0);

  		




  825
  825
  
    
	mityarm335x_i2c_init();

  		




  826
  826
  
    
	omap_sdrc_init(NULL, NULL);

  		




  827
  827
  
    
	omap_board_config = mityarm335x_config;

  		












  

    
      arch/arm/mach-omap2/devices.c
    
  





  1204
  1204
  
    
#ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE

  		




  1205
  1205
  
    
		.phy_id		= "0:01",

  		




  1206
  1206
  
    
#else

  		




  1207
  
  
    
		.phy_id		= "0:00",

  		




  
  1207
  
    
        .phy_id     = "0:01",

  		




  1208
  1208
  
    
#endif

  		




  1209
  1209
  
    

  		




  1210
  1210
  
    
	},

  		




  ......




  1214
  1214
  
    
#ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE

  		




  1215
  1215
  
    
		.phy_id		= "0:00",

  		




  1216
  1216
  
    
#else

  		




  1217
  
  
    
		.phy_id		= "0:01",

  		




  
  1217
  
    
        .phy_id     = "0:00",

  		




  1218
  1218
  
    
#endif

  		




  1219
  1219
  
    
	},

  		




  1220
  1220
  
    
};

  		




  ......




  1233
  1233
  
    
	.bd_ram_size		= SZ_16K,

  		




  1234
  1234
  
    
	.rx_descs               = 64,

  		




  1235
  1235
  
    
	.mac_control            = BIT(5), /* MIIEN */

  		




  1236
  
  
    
	.gigabit_en		= 1,

  		




  
  1236
  
    
	.gigabit_en		= 0,

  		




  1237
  1237
  
    
	.host_port_num		= 0,

  		




  1238
  1238
  
    
	.no_bd_ram		= false,

  		




  1239
  1239
  
    
	.version		= CPSW_VERSION_2,

  		




  ......




  1407
  1407
  
    
			am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);

  		




  1408
  1408
  
    
	platform_device_register(&am33xx_cpsw_mdiodevice);

  		




  1409
  1409
  
    
	platform_device_register(&am33xx_cpsw_device);

  		




  
  1410
  
    

  		




  
  1411
  
    
#define MII_MODE_ENABLE     0x0

  		




  
  1412
  
    
#define RMII_MODE_ENABLE    0x4 //5

  		




  
  1413
  
    
#define RGMII_MODE_ENABLE   0xA

  		




  
  1414
  
    
#define MAC_MII_SEL     0x650

  		




  
  1415
  
    
#define SMA2_ADDR 0x1320

  		




  
  1416
  
    

  		




  
  1417
  
    
	__raw_writel(RMII_MODE_ENABLE | 0xb0, //danm

  		




  
  1418
  
    
			AM33XX_CTRL_REGADDR(MAC_MII_SEL));

  		




  
  1419
  
    

  		




  
  1420
  
    
	__raw_writel(0x0, //danm

  		




  
  1421
  
    
			AM33XX_CTRL_REGADDR(SMA2_ADDR));

  		




  
  1422
  
    
	printk("%s  gmii_sel 0x%x\n",__func__,

  		




  
  1423
  
    
			__raw_readl(AM33XX_CTRL_REGADDR(MAC_MII_SEL))); //danm

  		




  
  1424
  
    

  		




  1410
  1425
  
    
	clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),

  		




  1411
  1426
  
    
			NULL, &am33xx_cpsw_device.dev);

  		




  1412
  1427
  
    
}

  		












  

    
      arch/arm/mach-omap2/mux33xx.c
    
  





  
  1
  
    

  		




  
  2
  
    

  		




  1
  3
  
    
/*

  		




  2
  4
  
    
 * AM33XX mux data

  		




  3
  5
  
    
 *

  		




  ......




  132
  134
  
    
		"gpmc_csn2", NULL, "mmc1_cmd", NULL,

  		




  133
  135
  
    
		NULL, NULL, NULL, "gpio1_31"),

  		




  134
  136
  
    
	_AM33XX_MUXENTRY(GPMC_CSN3, 0,

  		




  135
  
  
    
		"gpmc_csn3", NULL, NULL, "mmc2_cmd",

  		




  
  137
  
    
		"gpmc_csn3", NULL, "rmii2_crs_dv", "mmc2_cmd",

  		




  136
  138
  
    
		NULL, NULL, NULL, "gpio2_0"),

  		




  137
  139
  
    
	_AM33XX_MUXENTRY(GPMC_CLK, 0,

  		




  138
  140
  
    
		"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",

  		




  ......




  175
  177
  
    
		NULL, NULL, NULL, "gpio2_13"),

  		




  176
  178
  
    
	_AM33XX_MUXENTRY(LCD_DATA8, 0,

  		




  177
  179
  
    
		"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",

  		




  178
  
  
    
		NULL, NULL, "uart2_ctsn", "gpio2_14"),

  		




  
  180
  
    
		"uart5_txd", NULL, "uart2_ctsn", "gpio2_14"),

  		




  179
  181
  
    
	_AM33XX_MUXENTRY(LCD_DATA9, 0,

  		




  180
  182
  
    
		"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",

  		




  181
  
  
    
		NULL, NULL, "uart2_rtsn", "gpio2_15"),

  		




  
  183
  
    
		"uart5_rxd", NULL, "uart2_rtsn", "gpio2_15"),

  		




  182
  184
  
    
	_AM33XX_MUXENTRY(LCD_DATA10, 0,

  		




  183
  185
  
    
		"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",

  		




  184
  186
  
    
		NULL, NULL, NULL, "gpio2_16"),

  		




  ......




  221
  223
  
    
	_AM33XX_MUXENTRY(MMC0_DAT0, 0,

  		




  222
  224
  
    
		"mmc0_dat0", NULL, NULL, NULL,

  		




  223
  225
  
    
		NULL, NULL, NULL, "gpio2_29"),

  		




  224
  
  
    
	_AM33XX_MUXENTRY(MMC0_CLK, 0,

  		




  225
  
  
    
		"mmc0_clk", NULL, NULL, NULL,

  		




  
  226
  
    
	_AM33XX_MUXENTRY(MMC0_CLK, 0,   // skyline danm

  		




  
  227
  
    
		"mmc0_clk", "gpmc_a24", "uart3_ctsn", "uart2_rxd",

  		




  226
  228
  
    
		NULL, NULL, NULL, "gpio2_30"),

  		




  227
  
  
    
	_AM33XX_MUXENTRY(MMC0_CMD, 0,

  		




  228
  
  
    
		"mmc0_cmd", NULL, NULL, NULL,

  		




  
  229
  
    
	_AM33XX_MUXENTRY(MMC0_CMD, 0,   // skyline danm

  		




  
  230
  
    
		"mmc0_cmd", "gpmc_a25", "uart3_rtsn", "uart2_txd",

  		




  229
  231
  
    
		NULL, NULL, NULL, "gpio2_31"),

  		




  230
  232
  
    
	_AM33XX_MUXENTRY(MII1_COL, 0,

  		




  231
  233
  
    
		"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,

  		




  ......




  243
  245
  
    
		"mii1_rxdv", NULL, "rgmii1_rctl", NULL,

  		




  244
  246
  
    
		"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),

  		




  245
  247
  
    
	_AM33XX_MUXENTRY(MII1_TXD3, 0,

  		




  246
  
  
    
		"mii1_txd3", "d_can0_tx", "rgmii1_td3", NULL,

  		




  
  248
  
    
		"mii1_txd3", "d_can0_tx", "rgmii1_td3", "uart4_rxd",

  		




  247
  249
  
    
		"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),

  		




  248
  250
  
    
	_AM33XX_MUXENTRY(MII1_TXD2, 0,

  		




  249
  
  
    
		"mii1_txd2", "d_can0_rx", "rgmii1_td2", NULL,

  		




  
  251
  
    
		"mii1_txd2", "d_can0_rx", "rgmii1_td2", "uart4_txd",

  		




  250
  252
  
    
		"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),

  		




  251
  253
  
    
	_AM33XX_MUXENTRY(MII1_TXD1, 0,

  		




  252
  254
  
    
		"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",

  		




  ......




  256
  258
  
    
		"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),

  		




  257
  259
  
    
	_AM33XX_MUXENTRY(MII1_TXCLK, 0,

  		




  258
  260
  
    
		"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",

  		




  259
  
  
    
		"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),

  		




  
  261
  
    
		"mmc1_dat0", "uart1_dcdn", "mcasp0_aclkx", "gpio3_9"),

  		




  260
  262
  
    
	_AM33XX_MUXENTRY(MII1_RXCLK, 0,

  		




  261
  263
  
    
		"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",

  		




  262
  
  
    
		"mmc1_dat1", NULL, "mcasp0_fsx", "gpio3_10"),

  		




  
  264
  
    
		"mmc1_dat1", "uart1_dsrn", "mcasp0_fsx", "gpio3_10"),

  		




  263
  265
  
    
	_AM33XX_MUXENTRY(MII1_RXD3, 0,

  		




  264
  266
  
    
		"mii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5",

  		




  265
  267
  
    
		"mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"),

  		




  ......




  617
  619
  
    
	return 0;

  		




  618
  620
  
    
}

  		




  619
  621
  
    
#endif

  		




  
  622
  
    
 

  		












  

    
      drivers/net/ethernet/ti/cpsw.c
    
  





  448
  448
  
    
			mac_control |= BIT(15);

  		




  449
  449
  
    
		if (phy->duplex)

  		




  450
  450
  
    
			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/

  		




  451
  
  
    
		if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */

  		




  
  451
  
    
		if (phy->interface == PHY_INTERFACE_MODE_RMII) /* RGMII */

  		




  452
  452
  
    
			mac_control |= (BIT(15)|BIT(16));

  		




  453
  453
  
    
		*link = true;

  		




  454
  454
  
    
	} else {

  		




  ......




  457
  457
  
    
		mac_control = 0;

  		




  458
  458
  
    
	}

  		




  459
  459
  
    

  		




  
  460
  
    
  //  printk("danm 2 - mac control 0x%x 0x%p slave num %x, slave port 0x%x\n",mac_control,

  		




  
  461
  
    
  // danm             &slave->sliver->mac_control,slave->slave_num,slave_port);

  		




  
  462
  
    

  		




  460
  463
  
    
	if (mac_control != slave->mac_control) {

  		




  461
  464
  
    
		phy_print_status(phy);

  		




  462
  465
  
    
		__raw_writel(mac_control, &slave->sliver->mac_control);

  		




  ......




  571
  574
  
    
		return;

  		




  572
  575
  
    

  		




  573
  576
  
    
	phy_addr = phy->addr;

  		




  
  577
  
    
	phy->interface = PHY_INTERFACE_MODE_RMII;

  		




  574
  578
  
    

  		




  575
  579
  
    
	/* Disable 1 Gig mode support if it is not supported */

  		




  576
  580
  
    
	if (!pdata->gigabit_en)

  		















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