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upp clock
Added by Scott Whitney about 13 years ago
I have a userspace upp driver that I am trying to test in loopback mode. I am trying to loopback 1 line of a memory buffer (4096 bytes). I am polling the status register and when it catches the status registers for Q and I appear to have update correctly (current DMA address, line count, but I see a bus error in the interrupt status register. From the TI website someone saw this same problem and suggested it was a problem with the uPP xmit clock set to 110 MHz instead of 150 MHz(PLL1_SYSCLCK2), with the CPU at 300 MHz.
I see that the MityDSP is also using PLL1_SYSCLCK2 for the uPP xmit clock. Can someone verify if it is running at 150MHz? Thanks, Scott
Replies (2)
RE: upp clock - Added by Gregory Gluszek about 13 years ago
Hi Scott,
The fastest you will be able to get the uPP transmit clock to run with your setup is 75 MHz.
From the Upp User's Guide:
"The fixed divisor restricts the maximum speed of the I/O clock to one-fourth the device CPU clock speed."
\Greg
RE: upp clock - Added by Scott Whitney about 13 years ago
Greg,
Thanks for the reply. My question was more of how the clocks are setup on the board as a default. I suspected that the clocks were standard with the the uPP xmit clock 300/4 MHz. I found my problem with the uPP code in the end and it was not mis-configured clocks as was suggested by a poster on the TI web site. So now that I am transmitting in loopback I can go develop the complete driver. Scott
