Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

I found the solution!

Dear Jean-Pierre,
I am a newbie too in fpga programming: could you please post me a suggestion about the solution?
I have the same inconvenience.

Thank you very much in advance!

Michele

The learning curve for Xilinx tools is pretty darn steep anyway without jumping in at the deep end!

What I did is to add in the files I needed to my project starting with the top level VHDL file and the UCF file - I keep those in their own Code directory under source control and all the library files from Critical link in a mitylib directory nearby.

Then I add in the required modules from the mitylib directory - specifically:

• MityDSP_L138_pkg.vhd - the package file gives all the entity component declarations so you don't have to keep pasting that stuff in
• EMIFA_iface.vhd - this and the next two files are the main interface
• base_module.vhd
• core_version.vhd
• gpio.vhd - if you want gpio. There's also uart.ngc etc...

I ignored the xco file - it's probably for simulation and I didn't have the time to find out! Once you set all the settings recommended by Critical Link (likely twice - Xilinx ISE doesn't always seem to keep them) it should synthesise.

I can help with an example when I've time but it bears reading the example vhdl files and the package file to see how everything fits together. It isn't a 10 minute job!

Dear Conor,

I appreciate your help!

I have the suspect that the component emaclkdcm-Emifa_dcm is a digital clock manager of the emif clock, I'm not sure that I can eliminate it without pain.
Sure I will try not to include it in the top vhdl and see what happens, for example connecting the i_ema_clk signals directly to the EMIFA_iface.

Even if I have a doubt, now that I have synthesized something (the top module) and I have the RTL Schematic in front of me:
the Emifa_dcm has got this signals:
- as input i_ema_clk
- as output 3 bit of status STATUS[2:0} that goes to the base_module
- as output CLK_OUT1 , that become the new clock of emif inside the top module.
- as output LOCKED signal, that goes to the base module, maybe to assert a lock in phase of the DCM.

Maybe is a module that cleans up the clock signal from the emif interface of OMAP?

Let's try not to insert that in the top, connect the signal i_ema_clk directly to the modules and let's see what happens!

Thank you!

Michele

Hmmm. Not sure now because I'm afraid I didn't use the DCM at all! I didn't connect the i_ema_clk directly but via a global net (a BUFG). This is what the Critical Link industrialio example does rather than use a DCM. Indeed, their example has "-- TODO -- DCM???" in there so I guess they didn't need it!

emaclk_inst : BUFG
        port map (O => Ema_clk,
                  I => i_ema_clk);

It's totally up to you but I didn't have an issue with just buffering the clock. I'm new at FPGAs and didn't want to dabble with DCMs so early.

If it helps you at all, I'll attach my code. I'm pretty pedantic so the code should be easy enough to follow For example I use initial caps for all local signal declarations - VHDL is case insensitive but I still do it to keep myself sane...

The EMIFA DCM may not be required. If you do not require any other clocks than the 100 MHz (when running at 300 MHz CPU speed), then you can probably use a BUFG and skip the DCM.

The DCM does provide better skew management, but most designs meet timing without using it.

The output from the OMAP-L138 is 50%, so you don't really need the DCM to clean up the clocks.

If you need alternate clocks (from the clock synthesized outputs, or a divided clock), then the DCM can come in handy. However, the DCM can break lock if the clock is removed or changes frequency. This happens if you dynamically alter the CPU speed on the OMAP-L138 processor. In order to ensure that the DCM is reset, you need to monitor the status bits and apply the reset signals.

The base_module component provides some simple monitoring logic that will toggle the reset line if the DCM ever goes out of lock. You need to ensure that the generic to enable it is enabled when you instantiate it and of course hook up the signals correctly.

I will see if I have an example of using a DCM at the top level if you are interested.

In many example designs, we often don't use a DCM because we have no need for it.

Hope this helps.

-Mike