Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

The fpga can connect the gpio core to any pin you want. Gpio 144 should map to the first gpio core pin in the fpga image.

The .ucf file is used to map processor pins to net names in the vhdl.

MDK_2014-01-13/examples/industrial_io/fpga/vhdl/IndustrialIO_rev_C.ucf

NET "o_diode<0>"     LOC = "H14" | IOSTANDARD = LVCMOS33; #          J702-7      32_N
NET "o_diode<1>"     LOC = "E13" | IOSTANDARD = LVCMOS33; #          J702-15     24_N

And the vhd will connect the net names to the gpio core.

MDK_2014-01-13/examples/industrial_io/fpga/vhdl/IndustrialIO_top.vhd

gpio1 : gpio^M
    generic map (^M
      NUM_BANKS       => 1,^M
      NUM_IO_PER_BANK => 2^M
         )^M
         Port Map (^M
      clk             => ema_clk,^M
      i_ABus          => addr_r,^M
      i_DBus          => edi_r,^M 
      o_DBus          => edo_arm(CORE_GPIO_MODULE),^M
      i_wr_en         => wr_r,^M
      i_rd_en         => rd_r,^M
      i_cs            => arm_cs5_r(CORE_GPIO_MODULE),^M
      o_irq           => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR),^M
      i_ilevel        => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2),     ^M
      i_ivector       => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4),   ^M
      i_io            => "00",^M
      t_io            => open,^M 
      o_io            => o_diode,^M
      i_initdir       => "11",^M 
      i_initoutval    => "11"      ^M
         );^M

There is also a spreadsheet at MDK_2014-01-13/fpga/vhdl/OMAP-L138toFPGA.xlsx which maps the FPGA pin names to the SOMs pin names.

Hi Jonathan, thanks for the info... So I followed an example from a post a few years back (FPGA GPIO: toggle problem) and was able to get the GPIO going.

Regs, Tom

Can you link to the post? It may help me update the wiki page.

Hi Jonathan,

Here's the link

https://support.criticallink.com/redmine/boards/12/topics/2224

It's been a few years since my last FPGA project, so I was a bit rusty. What I benefited from most was looking at that posted source example and how it was modified. The wiki (which is good overall) has this... so an example of what is "proper" is what I needed

-----
An FPGA image with Critical Link's GPIO core built in properly.

See $MDK/examples/industrial_io/fpga/vhdl/IndustrialIO_top.vhd for an example of proper core usage.
    Note: Make sure that the GPIO core you add to your project has the IRQ level selected to match ARM usage so that core is enumerated by Linux (IRQ Level = 0 for a core should make Linux enumerate the core by default).
-----

So I've been working with the ISE project "build_dvi_rev_c", and initially made no modifications. It wasn't clear to me initially how to enable the GPIO core or what specific IndustrialIO_top.vhd modifications were needed to get it going (plus I'm really a verilog guy). Just running the base ISE example will yield the error of the missing gpiochip144. Anyway it's fairly obvious, but that along with the vhd example changes, the UCF file needs to be updated accordingly. Regs, Tom

Okay thanks Tom. I put that link in the wiki page to hopefully help people in the future.