Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hi Nigel,

The best guy to answer this question is on break this week and a good chunk of next week, can you wait for an answer?

Looking at the schematic, VCCPD3B4A is driven by a small compare/mux circuit that selects 2.5 V if VIO_4A is less than 2.5V, otherwise selects VIO_4A.

The same circuit logic is used for VCCPD8A, if VIO_8A is less than 2.5, 2.5 V is selected, otherwise VIO_8A is used.

I think the designer did this to specifically support 3.3V I/Os, but will check with him when he gets back into the office.

-Mike

No problem, it can wait a while.

Sounds like the SOM may have been catered for. Any thoughts on the dev kit or do you need to wait for the designer to get back?

Thanks.

Nigel.

Any update on whether the dev kit can be configured for 3.3v I/O?

Thanks,

Nigel.

Hi Nigel,

Below you will find the details to support additional IO standards. I believe this covers all the necessary details...

MityARM-5CSX VIO Support¶

VCCPD Power and Support for +3.0 or +3.3V Standards¶

The I/O banks were designed with 3.3V support in mind. The VCCPD rails are driven by the internal +2.5V regulator until the IO bank voltage goes above it, then it switches to the supplied +VIO input for the bank. Since banks 3B and 4A share VCCPD, the Altera rules must be followed: if +VIO_3B or +VIO_4A are higher than 2.5V, they both must match (3.0V or 3.3V). In this case, the VCCPD3B4A is supplied by +VIO_4A when above +2.5V for the IO voltage. It is expected that the +VIO_3B and +VIO_4A will be driven by the same supply when using these higher voltage standards. Avoid driving these two banks from separate supplies when the +VIO_3B or +VIO4A voltage is above +2.5V.

The lower voltage standards are supported as well by the built-in +2.5V minimum on the VCCPD rail. The IO standards at 2.5V and below can be mixed among the banks following Altera's rules.

The VCCPD8A uses another instance of that power switching to run that bank's voltage separately with the desired voltage standard specific to your application. Again, this will switch the VCCPD8A between a minimum of the +2.5V supply or a higher +VIO_8A voltage to support the standards above +2.5V.

+2.5V_VIO on the Development Board¶

The Dev Board uses +2.5V for the IO banks:

• VIO_4A
• VIO_3B
• VIO_8A
• TP4

It also uses this rail for a couple pull-ups on the PCIe interface. These will not cause an issue as they are weak pull-ups and mostly connected to bank 4A. The PERSTn signal does go to Bank5A on a lower voltage, but will be safe because it is a small enough current. The one area where there is a limitation concerns the X101 clock input. This is an LVDS clock source and may not be usable with higher IO voltage levels, but the boards will not be damaged.

If a different voltage standard is desired on the FPGA IOs, the voltage feedback can be adjusted on the switching supply U601 (R603, R613, and R616). Adjusting this will change the voltage on all three banks routed to the edge connector and will impact the IO signals on both HSMC connectors. The FPGA design will need to specify the appropriate IO standards on all three banks as well.

VREF Connection and Mixed IO Standards¶

The VREF connections are tied to voltage dividers that supply a reference voltage set to half the VIO voltage for each bank. This covers the most IO standards without consuming the limited edge connector pin resources. This does however, impede the use of mixed standards for supporting lower voltage input standards on a higher voltage bank. If an application requires this feature, please contact us for further support.

Testing¶

The dev board has been tested here with the full range of IO voltage standards to verify the VCCPD switching to prove out the design. There are no known issues with supporting the full range of IO voltage standards.

Follow Altera Guidelines for 3.0V and 3.3V IO Standards¶

Refer to Altera's documentation for additional details...

I/O Features in Cyclone V Devices http://www.altera.com/literature/hb/cyclone-v/cv_52005.pdf

• Table 5-10: MultiVolt I/O Support in Cyclone V Devices
• Page 5-11: I/O Design Guidelines for Cyclone V Devices
• Page 5-18: Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing
• etc.

Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing

To ensure device reliability and proper operation when you use the device for 3.3 V I/O interfacing, do not
violate the absolute maximum ratings of the device. For more information about absolute maximum rating
and maximum allowed overshoot during transitions, refer to the device datasheet.
Perform IBIS or SPICE simulations to make sure the overshoot and undershoot voltages are within
the specifications.

Please let us know if any additional insight is needed.

Thanks,
Adam

Thanks, very useful info. Will give it a try over the next couple of weeks.

Nigel.