Time limited SOF file question
Added by Rich Bagdazian over 10 years ago
I built a component into the FPGA that includes an instance of the Altera FIR II compiler.
At the end of the build, the final output is named: mityarm_5csx_dev_board_time_limited.sof
The file converter utility does not seem to be willing to convert this file to *.rbf format
I thought that designs that utilized ip cores that need full licensing would still run on the
target for an hour before self destructing. Do you know if there is some other way to use
time-limited designs on the mityArm board without having to resort to installing a licensed copy
of Quartus to do the builds?
Thanks!
Replies (3)
RE: Time limited SOF file question - Added by Michael Williamson over 10 years ago
Hi Rich,
This is an answer from our Altera FAE:
You can’t create .rbf files from time limited sof files. The concern is that you could put the .rbf in flash and reconfigure every hour to avoid paying for the IP. Some our 3rd parties have very expensive IP, and they are especially concerned about this.
You can configure the FPGA with the .sof file via JTAG, and run indefinitely while connected to Quartus through JTAG, or disconnect JTAG and run for some short period of time. This assumes you have access to the FPGA JTAG port.
Seems like this is a restriction placed on Altera and their third party vendors.
-Mike
RE: Time limited SOF file question - Added by Rich Bagdazian over 10 years ago
Thanks Mike,
Makes sense. I have a Terasic USB Blaster as shown in the attached PDF file.
What's the best way to interface the USB blaster to the white breakout connector on the MityArm Board?
Rich
| UsbBlaster.pdf (102 KB) UsbBlaster.pdf |
RE: Time limited SOF file question - Added by Rich Bagdazian over 10 years ago
Hi Mike,
Never mind my last post, I found the jtag breakout board in my original shipment.
-rb
