5CSX-H6-53B-RC with PCIe Hard IP (Root)
Added by Thomas Carpenter over 8 years ago
Hi,
We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently going over the pin mappings to make sure that we have enough pins.
I was reading through the design guide for the board but noticed something concerning about the PCIe connections. It states in that document that the PCIe reset (PERSTN) pin is on pin 21 (B5A_RX_B6_N), but says that this pin is not available for boards with 512MB or more of FPGA RAM.
Does this mean that it is not possible to use the PCIe root port on the 5CSX-H6-53B-RC board because it has 512MB of FPGA RAM?
We will require the 2GB of HPS RAM which only that version has, and we also need some FPGA RAM, but 64MB would be enough (I see there are some with 256MB which would also be fine). If it is not possible to use the PCIe port due to the conflicting pin requirements, is it possible to modify the MitySOM which has 512MB of FPGA RAM to only use 256MB of it (say remove the connection to the extra address bit) in order to allow the use of the PERSTN pin? Alternatively, is there a possibility to get a version of the MitySOM with 256MB of FPGA RAM, but 2GB of HPS RAM?
Thanks,
Tom.
Replies (4)
RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root) - Added by Adam Dziedzic over 8 years ago
Hi Thomas,
The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures the FPGA over the PCI Express bus interface. To use this mode, the PERSTN has only one option for the pin location. For the other use cases, the PERSTN pin can be assigned to other pin locations.
It sounds like you are planning to use the PCIe Root Port mode on the MitySOM. Please assign an available pin location in your design - I do not expect any issues.
Thanks,
Adam
RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root) - Added by Thomas Carpenter over 8 years ago
Hi Adam,
Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO can be used.
Would HPS_GPIO44 (pin244 on the MitySOM) be usable if I set up HPS loaning for that pin so that the FPGA can control it. We are basically using all of the I/O pin in the design bar 4 HPS pins (GPIO 44, 41, 40, and 37), so if the PERSTN pin can't be on pin 21, it would have to be one of those four. I suppose given that it is a very slow signal, it shouldn't be an issue.
Thanks,
Tom
RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root) - Added by Thomas Carpenter over 8 years ago
After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fine.
Thanks,
Tom.
RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root) - Added by Adam Dziedzic over 8 years ago
Hi Tom,
As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPGA I/O. A bank 8A pin is acceptable.
- Adam
