Differences in 5CSE-L2-3Y8-RC production runs?
Added by Lucas Uecker over 2 years ago
Hello. We've been doing some troubleshooting on prototype units that use the 5CSE-L2-3Y8-RC for DSP on the FPGA end and further treatment on the ARM CPU side and were puzzled by two units with fairly similar behavior on the analog front end have fairly different behavior in final output. At some point we joked about swapping SOM modules to test for differences... and then it turned out that the 'good' and 'meh' results traveled with the SOM modules after all. After some testing with our inventory of 5CSE-L2-3Y8-RC modules, we've found:
Rev C 'batch' 21-06-25: excellent output
Rev B 'batch' 19-06-24: not good output
Rev C 'batch' 21-08-08: not good output
Rev C 'batch' 22-01-07: close to 21-06-25 batch, but not quite as good
Rev C 'batch' 20-01-05: similar to 22-01-07
Rev C 'batch' 21-04-02: good output
As an example of "good":
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Versus "bad":
!MicrosoftTeams-image%20(3).png!
The only reasonable explanation of a difference between modules that I can think of is clock stability as our application involves a lock-in amplifier to monitor power levels at fairly specific frequencies. Any insight would be helpful.
Thanks.
Replies (1)
RE: Differences in 5CSE-L2-3Y8-RC production runs? - Added by Daniel Vincelette over 2 years ago
Hi Lucas,
That is an interesting finding, I'm not aware of any reports of lot to lot clock instabilities. Are you passing the HPS user clock to the FPGA as your main clock source for your FPGA design or is your FPGA being clocked by an external oscillator that is passed in from your baseboard? If you are feeding a clock from the HPS to the fabric and using that to drive a PLL, Intel does have an application note saying that they don't advise doing so because they did not characterize this case.
Here is the Guidance from Intel AN796
Cascading PLLs between the FPGA and HPS has not been characterized. Unless you perform the jitter analysis, do not chain the FPGA and HPS PLLs together as a stable clock coming out of the last PLL in the FPGA cannot be guaranteed. Output clocks from the HPS are not intended to be fed into PLLs in the FPGA.
Does your ADC have a test pattern that it could output, which would help narrow down the issue to the digital interface?
The other thing that I could see change with different SOMs is the FPGA lot, which can have slightly different timing. These different routing delays are handled by quartus in tandem with the project timing constraints. I've run into cases where I messed up my timing constraints (or didn't have any all together) for external interfaces, which made my design work fine on one SOM but have artifacts in the data on another.
Along those lines, in the past I've also run my design in a temperature chamber (both on a "good" unit and "bad" unit) and see if at the high or low end I can change the behaviors.
Dan
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