Clarification regarding LED 4 on MitySOM-5CSX DevKit
Added by Judy Mastracco 1 day ago
I am posting this on behalf of a customer.
I would like to verify that the schematic and pinout on MitySOM-5CSx_Pin-Out.xlsx, MitySOM-5CSx_Pin-Out.xlsx, MitySOM-5CSx_Pin-Out.xlsx documentation are up-to-date and specifically intended for the SoC model 5CSXFC6C6U23I7 used on the received MitySOM-5CSX evaluation board.
I’m asking because I created a small FPGA test project to deploy on the eval board, where the goal is simply to toggle a signal, but not the case ! I connected the main clock input to the output oscillator () 100MHZ HSMC2_CLK_P, which corresponds to pin T13 on the FPGA. However, when compiling with Quartus, I receive an error stating that this pin is not connected to a dedicated clock network (REFCLK/GCLK) accessible by the FPLL.
Thank you for your time and assistance.
Replies (1)
RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit - Added by Michael Williamson 1 day ago
I believe the spreadsheets are correct.
T13 is not connected to a dedicated clock input pin, needed to feed a REFCLK/CLK clock network. It is on pin 155 of the SOM connector.
HSMC2_CLK_P driving pin 155 of the Partial HSMC connector on the DevKit.
A coherent copy of this clock, GXB_REFCLK1_P, is fed to the SOM via pin 227 of the SOM interface, which is connected to pin P8 on the FPGA. You need to use that input if you are setting up a transceiver clocking interface to the Partial HSMC interface. We don't have a FPGA fabric general clock input pin connected to the partial HSMC connector. If you need to get a clock into the FPGA fabric, I would recommend you use the Full HSMC connector and drive HSMC1_CLKIN1_P or HSMC1_CLKIN2_P.
Please let me know if you still have questions.
-Mike
