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BN"Quick steps to Build" may be inaccurate in Building fpga 231 webpage

Added by Bob Nayar 13 days ago

The Building fpga 231 webpage (at https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_fpga_231) seems to have incorrect steps

For example, the Linux steps say:
Launch the Intel Embedded Command Shell from /opt/intelFPGA/23.1/embedded/embedded_command_shell.sh

There is no EMBEDDED folder in 23.1, only for 20.1

Bob N


Replies (22)

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 13 days ago

Bob,

Thanks for catching that. I've updated the page to point to the correct command shell that is available.

/opt/intelFPGA/23.1/nios2eds/nios2_command_shell.sh

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 13 days ago

Thanks, Mike.
Using this shell allows me to successfully do the "make generate_from_tcl"
HOWEVER,
when I do a "make all", I get this error:

<stuff deleted>
2026.09.18.12:56:25 Info: p0: *********************
2026.09.18.12:56:25 Info: p0:
2026.09.18.12:56:25 Info: p0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
2026.09.18.12:56:25 Info: m0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
ERROR: Cannot find sequencer/sequencer.elf
2026.09.18.12:56:27 Error: s0: Cannot find sequencer/sequencer.elf
2026.09.18.12:56:27 Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 943)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth dev_5cs_fpga_ddr_s0"
2026.09.18.12:56:27 Info: s0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
2026.09.18.12:56:27 Error: Generation stopped, 241 or more modules remaining
2026.09.18.12:56:27 Info: dev_5cs: Done "<b>dev_5cs</b>" with 86 modules, 77 files
2026.09.18.12:56:30 Error: qsys-generate failed with exit code 1: 3 Errors, 12 Warnings
2026.09.18.12:56:30 Info: Finished: <b>Create HDL design files for synthesis</b>
make: *** [Makefile:263: stamp/qsys.stamp] Error 3

Please advise.
I know that WSL is set to Version 1
Thanks.

Bob N

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 13 days ago

Bob,

Can you provide the output of the following in WSL:

which wsl
which make
which dos2unix
wsl -l -v

Can you also provide the full log rather than the trimmed version? The part you cut is where qsys-generate reports how it invoked the Nios II shell, and that's the piece I'm missing.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 13 days ago

nayar@GDZTHGC4E:~$ which wsl
/usr/bin/wsl
nayar@GDZTHGC4E:~$ which make
/usr/bin/make
nayar@GDZTHGC4E:~$ which dos2unix
/usr/bin/dos2unix
nayar@GDZTHGC4E:~$ wsl -l -v
Unknown command: -l

When I do “wsl -l -v” from CMD window, I get:
NAME STATE VERSION
  • Ubuntu-20.04 Running 1
    Ubuntu Stopped 2

Full logs:

nayar@GDZTHGC4E:/mnt/c/C10_CriticalLink/dev_5csx_h6_42a$ make all
qsys-generate dev_5cs.qsys --synthesis=VHDL
2026.09.18.14:37:13 Info: Saving generation log to /mnt/c/C10_CriticalLink/dev_5csx_h6_42a/dev_5cs/dev_5cs_generation.rpt
2026.09.18.14:37:13 Info: Starting: <b>Create HDL design files for synthesis</b>
2026.09.18.14:37:13 Info: qsys-generate /mnt/c/C10_CriticalLink/dev_5csx_h6_42a/dev_5cs.qsys --synthesis=VHDL --output-directory=/mnt/c/C10_CriticalLink/dev_5csx_h6_42a/dev_5cs/synthesis --family="Cyclone V" --part=5CSXFC6C6U23C7
2026.09.18.14:37:13 Info: Loading dev_5csx_h6_42a/dev_5cs.qsys
2026.09.18.14:37:13 Info: Reading input file
2026.09.18.14:37:13 Info: Adding check_0 [mem_check 1.0]
2026.09.18.14:37:13 Info: Parameterizing module check_0
2026.09.18.14:37:13 Info: Adding clk_100Mhz [clock_source 23.1]
2026.09.18.14:37:13 Info: Parameterizing module clk_100Mhz
2026.09.18.14:37:13 Info: Adding fpga_ddr [altera_mem_if_ddr3_emif 23.1]
2026.09.18.14:37:13 Info: Parameterizing module fpga_ddr
2026.09.18.14:37:13 Info: Adding hps_0 [altera_hps 23.1]
2026.09.18.14:37:13 Info: Parameterizing module hps_0
2026.09.18.14:37:13 Info: Adding mm_clock_crossing_bridge_0 [altera_avalon_mm_clock_crossing_bridge 23.1]
2026.09.18.14:37:13 Info: Parameterizing module mm_clock_crossing_bridge_0
2026.09.18.14:37:13 Info: Adding pio_0 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_0
2026.09.18.14:37:13 Info: Adding pio_1 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_1
2026.09.18.14:37:13 Info: Adding pio_2 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_2
2026.09.18.14:37:13 Info: Adding pio_3 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_3
2026.09.18.14:37:13 Info: Adding sysid_qsys [altera_avalon_sysid_qsys 23.1]
2026.09.18.14:37:13 Info: Parameterizing module sysid_qsys
2026.09.18.14:37:13 Info: Building connections
2026.09.18.14:37:13 Info: Parameterizing connections
2026.09.18.14:37:13 Info: Validating
2026.09.18.14:37:18 Info: Done reading input file
2026.09.18.14:37:19 Warning: dev_5cs.dev_5cs: Module dependency loop involving: "check_0" (mem_check 1.0), "hps_0" (altera_hps 23.1)
2026.09.18.14:37:19 Warning: dev_5cs.dev_5cs: Module dependency loop involving: "check_0" (mem_check 1.0), "hps_0" (altera_hps 23.1)
2026.09.18.14:37:19 Info: dev_5cs.check_0.wr: You have selected a length width that spans a larger transfer size than is addressable by the master port. Reducing the length width will improve the Fmax of this component.
2026.09.18.14:37:19 Warning: dev_5cs.check_0.rd_dis: Interrupt sender <b>rd_dis.csr_irq</b> is not connected to an interrupt receiver
2026.09.18.14:37:19 Warning: dev_5cs.check_0.wr_dis: Interrupt sender <b>wr_dis.csr_irq</b> is not connected to an interrupt receiver
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr.pll_bridge: <b>pll_bridge.pll_sharing</b> cannot be both connected and exported
2026.09.18.14:37:19 Info: dev_5cs.hps_0: HPS Main PLL counter settings: n = 0 m = 63
2026.09.18.14:37:19 Info: dev_5cs.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
2026.09.18.14:37:19 Info: dev_5cs.hps_0: ECC will be enabled in the preloader because an interface width of 24 or 40 has been chosen.
2026.09.18.14:37:19 Info: dev_5cs.pio_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.pio_1: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.pio_2: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.pio_3: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
2026.09.18.14:37:19 Info: dev_5cs.sysid_qsys: Time stamp will be automatically updated when this component is generated.
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr: <b>fpga_ddr.pll_sharing</b> must be exported, or connected to a matching conduit.
2026.09.18.14:39:16 Info: dev_5cs: Generating <b>dev_5cs</b> "<b>dev_5cs</b>" for QUARTUS_SYNTH
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has burstcount signal 1 bit wide, but the slave is 3 bit wide.
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has address signal 28 bit wide, but the slave is 26 bit wide.
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has byteenable signal 4 bit wide, but the slave is 0 bit wide.
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2026.09.18.14:39:21 Warning: hps_0.f2h_irq0: Cannot connect clock for <b>irq_mapper.sender</b>
2026.09.18.14:39:21 Warning: hps_0.f2h_irq0: Cannot connect reset for <b>irq_mapper.sender</b>
2026.09.18.14:39:21 Warning: hps_0.f2h_irq1: Cannot connect clock for <b>irq_mapper_001.sender</b>
2026.09.18.14:39:21 Warning: hps_0.f2h_irq1: Cannot connect reset for <b>irq_mapper_001.sender</b>
2026.09.18.14:39:25 Info: check_0: "<b>dev_5cs</b>" instantiated <b>mem_check</b> "<b>check_0</b>"
2026.09.18.14:39:26 Info: fpga_ddr: "<b>dev_5cs</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>fpga_ddr</b>"
2026.09.18.14:39:26 Info: hps_0: "Running for module: hps_0"
2026.09.18.14:39:26 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 63
2026.09.18.14:39:26 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
2026.09.18.14:39:27 Info: hps_0: ECC will be enabled in the preloader because an interface width of 24 or 40 has been chosen.
2026.09.18.14:39:27 Info: hps_0: "<b>dev_5cs</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>"
2026.09.18.14:39:27 Info: mm_clock_crossing_bridge_0: "<b>dev_5cs</b>" instantiated <b>altera_avalon_mm_clock_crossing_bridge</b> "<b>mm_clock_crossing_bridge_0</b>"
2026.09.18.14:39:27 Info: pio_0: Starting RTL generation for module 'dev_5cs_pio_0'
2026.09.18.14:39:27 Info: pio_0: Generation command is [exec /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/bin/perl I /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio - /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=dev_5cs_pio_0 --dir=/tmp/alt0714_6377484093029951334.dir/0003_pio_0_gen/ --quartus_dir=/home/nayar/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt0714_6377484093029951334.dir/0003_pio_0_gen//dev_5cs_pio_0_component_configuration.pl --do_build_sim=0 ]
2026.09.18.14:39:28 Info: pio_0: Done RTL generation for module 'dev_5cs_pio_0'
2026.09.18.14:39:28 Info: pio_0: "<b>dev_5cs</b>" instantiated <b>altera_avalon_pio</b> "<b>pio_0</b>"
2026.09.18.14:39:28 Info: pio_3: Starting RTL generation for module 'dev_5cs_pio_3'
2026.09.18.14:39:28 Info: pio_3: Generation command is [exec /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/bin/perl I /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio - /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=dev_5cs_pio_3 --dir=/tmp/alt0714_6377484093029951334.dir/0004_pio_3_gen/ --quartus_dir=/home/nayar/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt0714_6377484093029951334.dir/0004_pio_3_gen//dev_5cs_pio_3_component_configuration.pl --do_build_sim=0 ]
2026.09.18.14:39:29 Info: pio_3: Done RTL generation for module 'dev_5cs_pio_3'
2026.09.18.14:39:29 Info: pio_3: "<b>dev_5cs</b>" instantiated <b>altera_avalon_pio</b> "<b>pio_3</b>"
2026.09.18.14:39:29 Info: sysid_qsys: "<b>dev_5cs</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid_qsys</b>"
2026.09.18.14:39:30 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:30 Info: mm_interconnect_0: "<b>dev_5cs</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
2026.09.18.14:39:32 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: mm_interconnect_1: "<b>dev_5cs</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"
2026.09.18.14:39:33 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:33 Info: mm_interconnect_2: "<b>dev_5cs</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"
2026.09.18.14:39:33 Info: irq_mapper: "<b>dev_5cs</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
2026.09.18.14:39:33 Info: irq_mapper_001: "<b>dev_5cs</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper_001</b>"
2026.09.18.14:39:33 Info: rst_controller: "<b>dev_5cs</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"
2026.09.18.14:39:33 Info: check: "<b>check_0</b>" instantiated <b>altera_avalon_data_pattern_checker</b> "<b>check</b>"
2026.09.18.14:39:33 Info: csr: "<b>check_0</b>" instantiated <b>altera_avalon_mm_bridge</b> "<b>csr</b>"
2026.09.18.14:39:33 Info: gen: "<b>check_0</b>" instantiated <b>altera_avalon_data_pattern_generator</b> "<b>gen</b>"
2026.09.18.14:39:33 Info: rd: "<b>check_0</b>" instantiated <b>dma_read_master</b> "<b>rd</b>"
2026.09.18.14:39:34 Info: rd_dis: "<b>check_0</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>rd_dis</b>"
2026.09.18.14:39:34 Info: wr: "<b>check_0</b>" instantiated <b>dma_write_master</b> "<b>wr</b>"
2026.09.18.14:39:35 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:35 Info: mm_interconnect_0: "<b>check_0</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
2026.09.18.14:39:37 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: mm_interconnect_1: "<b>check_0</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"
2026.09.18.14:39:38 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:38 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:38 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:38 Info: mm_interconnect_2: "<b>check_0</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"
2026.09.18.14:39:39 Info: pll0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
2026.09.18.14:39:39 Info: p0: Generating clock pair generator
2026.09.18.14:39:40 Info: p0: Generating dev_5cs_fpga_ddr_p0_altdqdqs
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: *********************
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: Remember to run the dev_5cs_fpga_ddr_p0_pin_assignments.tcl
2026.09.18.14:39:59 Info: p0: script after running Synthesis and before Fitting.
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: *********************
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
2026.09.18.14:39:59 Info: m0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
ERROR: Cannot find sequencer/sequencer.elf
2026.09.18.14:40:01 Error: s0: Cannot find sequencer/sequencer.elf
2026.09.18.14:40:01 Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 943)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth dev_5cs_fpga_ddr_s0"
2026.09.18.14:40:01 Info: s0: "<b>fpga_ddr</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
2026.09.18.14:40:01 Error: Generation stopped, 241 or more modules remaining
2026.09.18.14:40:01 Info: dev_5cs: Done "<b>dev_5cs</b>" with 86 modules, 77 files
2026.09.18.14:40:02 Error: qsys-generate failed with exit code 1: 3 Errors, 12 Warnings
2026.09.18.14:40:02 Info: Finished: <b>Create HDL design files for synthesis</b>
make: *** [Makefile:263: stamp/qsys.stamp] Error 3

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 13 days ago

Bob,

Thanks for the log, I think this narrowed down your issue. Your Quartus is a Linux install running inside WSL, and Altera's nios2_command_shell.sh assumes WSL means a Windows install, so it puts the mingw32 toolchain on your PATH instead of the Linux one. Those directories don't exist in your install, so nios2-elf-gcc never gets found and the sequencer build silently produces nothing.

Launch the Nios II shell, then run the following:

which nios2-elf-gcc

My guess is this won't resolve. So export the following:

export PATH=$SOPC_KIT_NIOS2/bin/gnu/H-x86_64-pc-linux-gnu/bin:$PATH

Then run the following again:

which nios2-elf-gcc

This should now hopefully resolve. Then you can continue with the build.
- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 13 days ago

Actually, Mike.
I have Quartus 23.1 installed in both WSL and my Windows
The WSL install is in /home/nayar/intelFPGA/23.1 and the Windows install is in C:\intelFPGA\23.1std

and so, when I go a "which nios2-elf-gcc", I do get the correct resolved path:

nayar@GDZTHGC4E:/mnt/c/C10_CriticalLink/dev_5csx_h6_42a$ which nios2-elf-gcc
/home/nayar/intelFPGA/23.1std/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/nios2-elf-gcc

So yeah, even after the export PATH commmand, I get the same issue

Bob N

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 13 days ago

Bob,

The following is my guess:

You needed WSL 1 for the Windows Quartus Nios II shell, but now that you've moved to a Linux Quartus install inside WSL, WSL 1 is likely working against you. You already have an Ubuntu distro on WSL 2, so it may be worth trying the Linux build over there.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 13 days ago

Mike, when you asked to do this command:

which nios2-elf-gcc

did you mean "which nios2-elf-gcc. exe " ?

Bob N

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 13 days ago

I am asking that because

"which nios2-elf-gcc" gives me nothing

but "which nios2-elf-gcc.exe" gives me /mnt/c/intelFPGA/23.1std/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/nios2-elf-gcc.exe

Same for "Which quartus.exe".

Is this a clue?

BN

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 12 days ago

I re-installed WSL (deleting the Linux Quartus install), this time using Ubuntu 22.04
(I did not have the option of installing Ubuntu 20 and CriticalLink's website says that 22 is OK)

Try to start from the beginning now, because I want to document the steps.

I was able to progress in 'generate_from_tcl' by adding '.exe' to the tail of the following executables in the Makefile:
quartus_sh
qsys-script

My next question is:
Can these error messages below be ignored during the 'generate_from_tcl' process?:

ERROR: Device family can not be determined
ERROR: The minimum delay difference between CK and DQS must be less than or equal to the maximum delay difference between CK and DQS
Error: set_interface_property hps_io EXPORT_OF hps_0.hps_io: No interface named hps_0.hps_io.

Trying to see if these errors are causing the 'generate_from_tcl' process to fail like this:
make1: * [Makefile:563: qsys_generate_qsys] Error 1
make1: Leaving directory '/mnt/c/C10_CriticalLink/dev_5csx_h6_42a'
make: * [Makefile:575: generate_from_tcl] Error 2

Nevertheless, the QSYS file(s) are still generated

BN

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 11 days ago

Another that I get during 'generate_from_tcl' is:

Error: set_project_property DEVICE '5CSXFC6C6U23C7': The device '5CSXFC6C6U23C7' is unknown; reverted to the default device.

This error does not make my sense to me.
The consequences of this error seen when I do a 'make all' from this point on and I see this error:

Error: hps_0: Selected device '5CEBA2F17A7' is not an SoC device. Please choose a valid SoC device to use the Hard Processor System.

I don't know why I am getting the The device '5CSXFC6C6U23C7' is unknown error in the first place.

BN

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 9 days ago

Bob,

I have setup a Windows 11 machine here to try to match your configuration. Since you are trying to install Quartus in a way not recommended by Altera you are running into pathing issues I mentioned above where the Altera's scripts see WSL and assume a Windows installation where as that is not how you have it installed.

In order to get a Linux Installation working in WSL, you have to fix this pathing issue in the script to stop trying to source the Windows binaries (since you have the Linux version installed).

The best hack I have found to get your setup to work would be to symlink the Linux binaries to have .exe so it matches what the script expects. Run this in the Nios II command shell so the environment variable is properly set:

cd "$SOPC_KIT_NIOS2/bin/gnu/H-x86_64-pc-linux-gnu/bin" || exit
for f in *; do [ -f "$f" ] && [ -x "$f" ] && ln -s "$f" "$f.exe"; done
cd "$SOPC_KIT_NIOS2/sdk2/bin" || exit
for f in *; do [ -f "$f" ] && [ -x "$f" ] && ln -s "$f" "$f.exe"; done

Doing the above allows me to compile our reference design start to finish in a Linux Quartus Install running inside WSL.

My recommendation would be to follow Altera's installation instructions for installing Windows Quartus version in Windows.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 9 days ago

Mike Fiorenza wrote in RE: "Quick steps to Build" may be inaccurate in Building ...:

Bob,

I have setup a Windows 11 machine here to try to match your configuration. Since you are trying to install Quartus in a way not recommended by Altera you are running into pathing issues I mentioned above where the Altera's scripts see WSL and assume a Windows installation where as that is not how you have it installed.

- Mike

Mike: I have removed the Linux installation from WSL.
I have Quartus installed only on Windows now.

BN

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 9 days ago

Mike: I actually have an interesting data point.

I can build the FPGA image completely using the Quartus 23.1std application in Windows

I think what happened earlier was that I had installed Quartus inside WSL as well as Windows and that's what caused all the problems to start with.

My main question to you know is:

What gets generated from the 'make generate_from_tcl' followed by 'make all' that I cannot generate using the Quartus 23.1std Windows application?

BN

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 9 days ago

Bob,

You were right, and the problem is on our end. Our wiki's Windows instructions for the Makefile flow cannot work, and following them is what sent you down this path. Sorry for the runaround.

The short version is that the Makefile is a Unix makefile. Line 10 is SHELL := /bin/bash and it shells out to sed, grep, find and so on throughout. On Windows the only bash is WSL, and the Nios II Command Shell our page points you at is just a wrapper that runs wsl bash -c. But Quartus launched from inside WSL cannot resolve the device, which is exactly the "'5CSXFC6C6U23C7' is unknown; reverted to the default device" you were seeing. I reproduced that here on a Windows 11 box running Quartus 23.1 Standard with Cyclone V device support definitely installed, so it was never a missing device pack. The same tools run natively on Windows resolve the part correctly.

So your instinct to build in the GUI was the right one. Here is the full flow, which I have now run end to end on a Windows machine:

1. FPGA image

Build the project in the Quartus GUI as you are doing. Then produce the .rbf either from File > Convert Programming Files, or from a normal Windows command prompt:

quartus_cpf -c output_files/dev_5cs.sof output_files/dev_5cs.rbf

Both the .sof and the .rbf should end up in output_files/.

2. Bootloader (u-boot + preloader)

This is the piece the GUI cannot produce, but you can build it in the WSL you already have. It does not use Quartus at all, so none of the WSL pathing problems apply. It only needs the hps_isw_handoff folder your Quartus build already created.

One time setup inside WSL:

sudo apt update
sudo apt install -y git make python-is-python3 bc bison flex libssl-dev
cd /tmp
wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf.tar.xz
sudo tar xf gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf.tar.xz -C /opt

Then, from your project directory in WSL:

export PATH=/opt/gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf/bin:$PATH
make uboot

That produces software/preloader/u-boot-socfpga/u-boot-with-spl.sfp.

Two things worth knowing. The Makefile hardcodes the arm-none-linux-gnueabihf- prefix, so Ubuntu's gcc-arm-linux-gnueabihf package will not work, you need ARM's toolchain as above. And run make uboot from the full project directory, not from a folder containing only your build outputs, since the Makefile needs the .qsys present to configure itself.

3. SD card

make sd_image

This takes the u-boot image, the u-boot environment, the .rbf and a Yocto root filesystem tarball that you copy into the software/preloader folder. Note that our wiki currently names that tarball mitysom-image-base-mitysom-5cs.tar.gz but the Makefile looks for mitysom-image-base-mitysom-c5.tar.gz. If the name does not match, make just reports a missing tarball and does nothing.

What the Makefile handles that the GUI does not

To answer your earlier question directly: for the FPGA image itself, nothing. The GUI does the same work, qsys generation, synthesis, fitting and assembly. The Makefile is automation around it.

What it adds beyond that:

  • The .rbf conversion, which is just quartus_cpf as above.
  • U-Boot and the preloader, covered in step 2. This is the real one, and it is why you still need WSL for part of the flow.
  • uBootMMCEnv.txt, the U-Boot environment for your specific SoM variant.
  • Project regeneration. make generate_from_tcl rebuilds the .qsf, .qpf, dev_5cs_top.vhd and dev_5cs.qsys from the tcl scripts, parameterized by the SOM_MODEL variable at the top of the Makefile. That is how we produce the project for each of the six SoM variants we support.

On that last one, since you mentioned early on that you had made changes in Platform Designer: generate_from_tcl runs scrub_clean first, which deletes the .qsys, .qsf, .qpf, the generated top level and output_files. Any edits you have made in Platform Designer or to the pin assignments will be lost. If you already have a working project for your module, you do not need to run it at all.

I will update the wiki pages to reflect all of this. Thanks for sticking with it, you turned up several real problems in our documentation along the way.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 9 days ago

Thank you so much for this post, Mike.
It answers a ton of questions.

Bob N

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 8 days ago

Mike: I got all the steps done but I am stuck at the last one ( make sd_image )

Apparently, the "make_sd.sh" script does not seem to like Line-Feed/Carriage-Return symbols.
Look at the errors below:

bobnayar@GDZTHGC4E:/mnt/c/C10_CriticalLink/Alfred_Test$ make sd_image
_software/preloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator/cv_bsp_generator.py i hps_isw_handoff/dev_5cs_hps_0 -o software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/sdram_config.h...
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/pinmux_config.h...
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/pll_config.h
Reading file: hps_isw_handoff/dev_5cs_hps_0/dev_5cs_hps_0.hiof...
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/iocsr_config.h...
make CROSS_COMPILE=arm-none-linux-gnueabihf DEVICE_TREE=socfpga_mitysom5csx-h6-42a_devkit -C software/preloader/u-boot-socfpga socfpga_mitysom5cs_defconfig
make1: Entering directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga' #
  1. configuration written to .config #
    make1: Leaving directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga'
    make CROSS_COMPILE=arm-none-linux-gnueabihf- DEVICE_TREE=socfpga_mitysom5csx-h6-42a_devkit -C software/preloader/u-boot-socfpga -j 48
    make1: Entering directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga'
    scripts/kconfig/conf --syncconfig Kconfig
    CFG u-boot.cfg
    GEN include/autoconf.mk.dep
    CFG spl/u-boot.cfg
    GEN include/autoconf.mk
    GEN spl/include/autoconf.mk
    ENVC include/generated/env.txt
    UPD include/generated/timestamp_autogenerated.h
    ENVP include/generated/env.in
    ENVT include/generated/environment.h
    CC arch/arm/mach-socfpga/wrap_pll_config.o
    AR arch/arm/mach-socfpga/built-in.o
    CC env/common.o
    CC cmd/version.o
    AR env/built-in.o
    AR cmd/built-in.o
    CC lib/efi_loader/dtbdump.o
    CC lib/efi_loader/initrddump.o
    LD lib/efi_loader/initrddump_efi.so
    LD lib/efi_loader/dtbdump_efi.so
    OBJCOPY lib/efi_loader/initrddump.efi
    OBJCOPY lib/efi_loader/dtbdump.efi
    LD u-boot
    OBJCOPY u-boot.srec
    OBJCOPY u-boot-nodtb.bin
    SYM u-boot.sym
    CAT u-boot-dtb.bin
    CC spl/common/spl/spl.o
    CC spl/arch/arm/mach-socfpga/wrap_pll_config.o
    CC spl/arch/arm/mach-socfpga/wrap_iocsr_config.o
    CC spl/arch/arm/mach-socfpga/wrap_pinmux_config.o
    CC spl/arch/arm/mach-socfpga/wrap_sdram_config.o
    AR spl/common/spl/built-in.o
    AR spl/arch/arm/mach-socfpga/built-in.o
    LD spl/u-boot-spl
    OBJCOPY spl/u-boot-spl-nodtb.bin
    SYM spl/u-boot-spl.sym
    CAT spl/u-boot-spl-dtb.bin
    COPY spl/u-boot-spl.bin
    MKIMAGE spl/u-boot-spl.sfp
    COPY u-boot.bin
    MKIMAGE u-boot.img
    MKIMAGE u-boot-dtb.img
    SOCBOOT u-boot-with-spl.sfp
    OFCHK .config
    make1: Leaving directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga'
    sed "s/mitysom5csx/mitysom5csx/" software/preloader/uBootMMCEnv.txt.orig >software/preloader/uBootMMCEnv.txt
    sed -i "s/dev_5csx_h6_42a/dev_5cs/" software/preloader/uBootMMCEnv.txt
    echo "clmodelnum=5CSX-H6-42A-RC" >> software/preloader/uBootMMCEnv.txt
    software/preloader/u-boot-socfpga/tools/mkenvimage -s 8192 -o software/preloader/ubootenv.bin software/preloader/uBootMMCEnv.txt
    ./software/preloader/make_sd.sh -d CycloneV -u software/preloader/u-boot-socfpga/u-boot-with-spl.sfp -e software/preloader/ubootenv.bin -f output_files/dev_5cs.rbf -o software/preloader/sd_card.img software/preloader/mitysom-image-base-mitysom-c5.tar.gz
    ./software/preloader/make_sd.sh: line 2: $'\r': command not found
    ./software/preloader/make_sd.sh: line 5: $'\r': command not found
    ./software/preloader/make_sd.sh: line 9: $'\r': command not found
    ./software/preloader/make_sd.sh: line 13: syntax error near unexpected token `$'\r''
    '/software/preloader/make_sd.sh: line 13: `die()
    make: *** [Makefile:661: software/preloader/sd_card.img] Error 2_

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 8 days ago

OK. Ignore the last post. I used DOS2UNIX to fix the make_sd.sh script

Now when I did the make sd_image, I got the 1 GB image file, but I also got an error at the end:

bobnayar@GDZTHGC4E:/mnt/c/C10_CriticalLink/Alfred_Test$ make sd_image
software/preloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator/cv_bsp_generator.py i hps_isw_handoff/dev_5cs_hps_0 -o software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/sdram_config.h...
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/pinmux_config.h...
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/pll_config.h
Reading file: hps_isw_handoff/dev_5cs_hps_0/dev_5cs_hps_0.hiof...
Generating file: software/preloader/u-boot-socfpga/board/cl/mitysom-5cs/qts/iocsr_config.h...
make CROSS_COMPILE=arm-none-linux-gnueabihf DEVICE_TREE=socfpga_mitysom5csx-h6-42a_devkit -C software/preloader/u-boot-socfpga socfpga_mitysom5cs_defconfig
make1: Entering directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga' #
  1. configuration written to .config #
    make1: Leaving directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga'
    make CROSS_COMPILE=arm-none-linux-gnueabihf- DEVICE_TREE=socfpga_mitysom5csx-h6-42a_devkit -C software/preloader/u-boot-socfpga -j 48
    make1: Entering directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga'
    scripts/kconfig/conf --syncconfig Kconfig
    CFG u-boot.cfg
    GEN include/autoconf.mk.dep
    CFG spl/u-boot.cfg
    GEN include/autoconf.mk
    GEN spl/include/autoconf.mk
    ENVC include/generated/env.txt
    UPD include/generated/timestamp_autogenerated.h
    ENVP include/generated/env.in
    ENVT include/generated/environment.h
    CC arch/arm/mach-socfpga/wrap_pll_config.o
    AR arch/arm/mach-socfpga/built-in.o
    CC env/common.o
    CC cmd/version.o
    AR env/built-in.o
    AR cmd/built-in.o
    CC lib/efi_loader/dtbdump.o
    CC lib/efi_loader/initrddump.o
    LD lib/efi_loader/initrddump_efi.so
    LD lib/efi_loader/dtbdump_efi.so
    OBJCOPY lib/efi_loader/initrddump.efi
    OBJCOPY lib/efi_loader/dtbdump.efi
    LD u-boot
    OBJCOPY u-boot.srec
    OBJCOPY u-boot-nodtb.bin
    SYM u-boot.sym
    CAT u-boot-dtb.bin
    CC spl/common/spl/spl.o
    CC spl/arch/arm/mach-socfpga/wrap_pll_config.o
    CC spl/arch/arm/mach-socfpga/wrap_iocsr_config.o
    CC spl/arch/arm/mach-socfpga/wrap_pinmux_config.o
    CC spl/arch/arm/mach-socfpga/wrap_sdram_config.o
    AR spl/common/spl/built-in.o
    AR spl/arch/arm/mach-socfpga/built-in.o
    LD spl/u-boot-spl
    OBJCOPY spl/u-boot-spl-nodtb.bin
    SYM spl/u-boot-spl.sym
    CAT spl/u-boot-spl-dtb.bin
    COPY spl/u-boot-spl.bin
    MKIMAGE spl/u-boot-spl.sfp
    COPY u-boot.bin
    MKIMAGE u-boot.img
    MKIMAGE u-boot-dtb.img
    SOCBOOT u-boot-with-spl.sfp
    OFCHK .config
    make1: Leaving directory '/mnt/c/C10_CriticalLink/Alfred_Test/software/preloader/u-boot-socfpga'
    sed "s/mitysom5csx/mitysom5csx/" software/preloader/uBootMMCEnv.txt.orig >software/preloader/uBootMMCEnv.txt
    sed -i "s/dev_5csx_h6_42a/dev_5cs/" software/preloader/uBootMMCEnv.txt
    echo "clmodelnum=5CSX-H6-42A-RC" >> software/preloader/uBootMMCEnv.txt
    software/preloader/u-boot-socfpga/tools/mkenvimage -s 8192 -o software/preloader/ubootenv.bin software/preloader/uBootMMCEnv.txt
    ./software/preloader/make_sd.sh -d CycloneV -u software/preloader/u-boot-socfpga/u-boot-with-spl.sfp -e software/preloader/ubootenv.bin -f output_files/dev_5cs.rbf -o software/preloader/sd_card.img software/preloader/mitysom-image-base-mitysom-c5.tar.gz
    0+0 records in
    0+0 records out
    0 bytes copied, 0.0006485 s, 0.0 kB/s
    Creating partitions
    stdin:1: libguestfs: error: /usr/bin/supermin exited with error status 1.
    To see full error messages you may need to enable debugging.
    Do:
    export LIBGUESTFS_DEBUG=1 LIBGUESTFS_TRACE=1
    and run the command again. For further information, read:
    http://libguestfs.org/guestfs-faq.1.html#debugging-libguestfs
    You can also run 'libguestfs-test-tool' and post the complete output
    into a bug report or message to the libguestfs mailing list.
    make: *** [Makefile:661: software/preloader/sd_card.img] Error 1

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 8 days ago

Bob,

Thanks for posting the full output. I was able to reproduce both of these here.

1. Line endings

The repository stores make_sd.sh with Unix line endings. Git for Windows converts text files to Windows line endings on checkout by default (its core.autocrlf=true setting), which is most likely how your copy got them. dos2unix was the right fix.

One more file has the same problem, and this one fails silently: software/preloader/uBootMMCEnv.txt.orig. The Makefile builds the U-Boot environment, ubootenv.bin, from it. With Windows line endings, every variable ends up with a trailing carriage return, and U-Boot won't strip it. For example, mmcfpgaloc becomes /dev_5cs.rbf plus a carriage return. Please run:

dos2unix software/preloader/uBootMMCEnv.txt.orig

make sd_image regenerates ubootenv.bin from that file on every run, so nothing else needs cleaning up. Those are the only two files in the SD card flow that are affected. make handles the Makefile's line endings fine, and u-boot-socfpga was cloned inside WSL, so it already has Unix line endings.

2. libguestfs / supermin error

make_sd.sh builds the image with libguestfs. libguestfs does its work inside a small helper virtual machine, which it boots using the Linux kernel installed in /boot. WSL doesn't put a kernel there, so there is nothing to boot. If you run with LIBGUESTFS_DEBUG=1, the underlying message is "supermin: failed to find a suitable kernel". This is why our SD card page lists a Linux host.

You can work around it by installing a kernel package inside WSL just for libguestfs to use. WSL never boots it.

sudo DEBIAN_FRONTEND=noninteractive apt install -y linux-image-generic
sudo chmod a+r /boot/vmlinuz*
make sd_image

I ran exactly this here on Ubuntu 22.04 under WSL 1, as a regular user, from a project on /mnt/c. I then checked the resulting sd_card.img: it has the three partitions, with the .rbf on the FAT partition, u-boot-with-spl.sfp on the A2 partition and the environment right after the MBR, all matching the build outputs.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 8 days ago

Thank again, Mike.
I was able to generate a new SD image after going through your steps.

Can you please look at the attached screenshot to see if any of the messages at the end of the long make sd_image process mean anything negative?
Thanks.

Bob N

messages_end_of_make_sd_image.jpg (196 KB) messages_end_of_make_sd_image.jpg

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 8 days ago

Bob,

The output attached appears to be of apt install linux-image-generic not make sd_image. If you're referring to the mdadm warnings at the end of the apt install, yes these are fine it's just stating that you don't have Linux RAID setup on your host (which is irrelevant here).

If make sd_image finished with "Generating .md5 file" and no make error with the sd_card.img in software/preloader then your image should be good.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 8 days ago

Thank you so much, Mike.
My SD card image works well

BN

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