Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Bob,

Is there a reason not to use h2f_reset the way the reference design does? Everything in the design hangs off it, the DDR controller's global and soft resets, the clock crossing bridge, the PIOs, sysid and the memory checker. If your logic lives in Platform Designer, connecting its reset sink to hps_0.h2f_reset gets you the same treatment, and the tool inserts a reset synchronizer per clock domain so the deassertion is clean.

If you would rather have a push button to reset the fabric on demand, you can do that as well. SW1 through SW3 are currently assigned to HPS GPIO (37, 40 and 41), so you would need to unassign one in the HPS Peripheral Pins Multiplexing tab and switch it to LoanIO. That gives you h2f_loan_io_in[nn] in the fabric, which you can feed into a Reset Bridge the same way.

- Mike

Mike,

Is the hps_0.h2f_reset active-high or active-low?

My logic design lives outside of the Platform Designer.
So, if I try to export hps_0.h2f_reset I get other errors, because exporting removes all the other connections that hps_0.h2f_reset is going to.
Can I use clk_100mhz_clk_reset instead?
It is fed by hps_0.h2f_reset.

BN

Bob,

h2f_reset is active low at the HPS, the pin is h2f_rst_n. Platform Designer handles the polarity for you though, so with a Reset Bridge you choose what you get: leave Active low reset unchecked and your exported port is active high.

For your case, add a Reset Bridge, connect hps_0.h2f_reset to its input, and export the bridge output to the top level. That avoids the problem you hit, since exporting the bridge output does not disturb the existing h2f_reset connections.

You could export clk_100Mhz.clk_reset instead, nothing else in the design connects to it and it is fed from h2f_reset, so it would work. I would still use the bridge, since it gives you explicit control over polarity and the synchronizer rather than relying on what the clock source passes through.

- Mike