Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

The default dev_5cs_top.vhd file for the MitySom-5CSx board has LED1, LED2 and LED3 driven by HPS GPIO signals, GPIO 50, GPIO 49 and GPIO 48 respectively.
In order to drive these LEDs from FPGA fabric logic, I took the following steps:

1) In Platform Designer, I disabled GPIOs 48, 49 and 50 from the Mux Table and enabled the loan IOs 48, 49 and 50
2) Exported h2f loan IO conduit
3) Enabled the 'Enable general purpose signals' in the FPGA Interfaces tab (not sure if this is needed or not)
4) Generated the HDL
5) Connected loan IOs 48, 49 and 50 of the dev_5cs qsys instantion to LED3, LED2 and LED1 respectively.
6) Connected loan conduit signals like this:
signal loan_io_in : std_logic_vector(66 downto 0);
signal loan_io_out : std_logic_vector(66 downto 0);
signal loan_io_oe : std_logic_vector(66 downto 0);

<qsys instantiation>
loan_io_in => loan_io_in,
loan_io_out => loan_io_out,
loan_io_oe => loan_io_oe,

7) wrote this RTL:

loan_io_out(48) <= '0'; -- LED 3
   loan_io_oe(48)  <= '1';
   loan_io_out(49) <= '0'; -- LED 2
   loan_io_oe(49)  <= '1';
   loan_io_out(50) <= '0'; -- LED 1
   loan_io_oe(50)  <= '1';

Still the LEDs don't turn on.
Pulling those signals low should turn them on.

What am I doing wrong?

BN