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KSZ RGMII Phy Design Considerations

Critical Link has used the KSZ series of RGMII Phys on a large number of designs including our MitySOM-5CSX, MitySOM-335x, MitySOM-AM57x, MitySOM-A10S and many other baseboard designs. Over the course of those implementations, and part shortages, we have found a number of design considerations that we felt could assist our customers with their design challenges.

IO Voltages

Phy IO Voltage Notes
KSZ9021 2.5V or 3.3V (!) For 5CSX this can't be used on the bank 7B (1.8V bank) pins
KSZ9031 1.8V, 2.5V, or 3.3V
KSZ9131 1.8V, 2.5V, or 3.3V

KSZ Phy 1.2V Current Requirements

Below is a breakdown of each of the 3 "compatible" KSZ phys and their power consumption:

Phy Speed 1.2V Current
KSZ9021 100 158mA
KSZ9021 Gigabit 563mA (!)
KSZ9031 100 64mA
KSZ9031 Gigabit 221mA
KSZ9131 100 69mA
KSZ9131 Gigabit 220mA

For future reference it should be noted that the KSZ9021 in a Gigabit implementation would NOT be recommended with either a MOSFET or LDO due to the ~1.2W of power dissipation needed, assuming a 3.3V input to the MOSFET/LDO.

As a short example if the NTF6P02 is used it has a 71C/watt thermal resistance with a 1" square PCB heat pad. At the 1.2W power usage (Based on a 3.3V input to 1.2V output) needed for KSZ9021 at Gigabit operation, 563mA, that gives a temperature rise of 85C. For an Industrial (RI) design we need to support an ambient temperature up to 85C which would put the MOSFET at a temperature of 170C, it is rated for a maximum operating temperature of 150C. Most LDO's are only rated to 125C operating which means we are then 45C above operating spec.

As such a DC-DC converter would be needed instead for the case of a KSZ9021 running at Gigabit with a 3.3V input.

KSZ Phy 1.2V Power Supply Options

There are 3 main power supply options for the 1.2V supply inputs to the KSZ Phys discussed below. Additionally the attached "ANLAN206" document from Micrel discusses the MOSFET and multiple DC-DC supply options and is overall a great reference on this topic.

MOSFET Controlled by the Phy (LDO_O output) (3.3V MOSFET Input Option Only)

Per this Microchip issue (https://microchipsupport.force.com/s/article/Common-Schematic-Errors-with-KSZ9031-on-chip-LDO-Controller-Circuit) two recommendations to followed when using the MOSFET
  • For a MOSFET a 100k ohm resistor from Gate (pin 1) to source (Pin 3)
  • There should NOT be a ferrite bead between the MOSFET 1.2V output and the AVDDL net, it should be directly connected.
  • Both are also documented in the KSZ9031 power supply design application note

Due to the necessary VGS threshold voltages required for the MOSFET the input to the MOSFET must be 3.3V (or higher) due to the voltage level driven by the Phy to the Gate of the MOSFET. If an input lower than 3.3V is used for the MOSFET source it is unlikely the MOSFET will be able to pass enough current through for the Phy to operate.

P-Channel MOSFET Options (with appropriate VGS)
  • NTF6P02 or NVF6P02
  • STN5PF02V (obsolete)
  • FDT434P (obsolete)

(!) Note that other MOSFETS may offer sufficient current capabilities and STATED low VGS, i.e. 1V, in the same package but most do NOT have a low enough VGS to work with the Phy at the output currents required. Some specify the output current at the stated VGS of only 1mA.

Note that if a 5V input were used its more than likely that the power dissipation will exceed the maximum of the MOSFET.

External LDO

Critical Link has used an external LDO in place of the Phy controlled MOSFET. As documented below it is possible to create a PCB design that will support either the LDO or MOSFET populations.

Industrial Temperature 500mA or Greater LDO POTENTIAL Options With MOSFET (SOT-223) Compatible Footprints:
  • LD1117S12CTR
  • AP2114H-1.2TRG1
  • ZLDO1117G12TA
  • LDI1117-1.2H

Note that unlike with the MOSFET most LDO's will recommend a minimum load on the output. In this case an additional load resistor will need to be added.

When using an LDO care should be selected to ensure the PCB is able to dissipate the power burned by the LDO, as noted in the "Current" section above.

External DC-DC Converter

Three different DC-DC implementations are documented in the ANLAN206-UNG, attached, from Micrel.

A DC-DC converter is a more costly implementation option but typically allows wider input voltage options and reduced heat dissipation concerns.

Support both an LDO and MOSFET (3.3V input) on a single design

For designs where an LDO or MOSFET are acceptable, in regards to the power dissipation requirements of the 1.2V supply, a compatible footprint/layout can be created for both to help with any part availability issues:

  1. Use the SOT-223 package
  2. Connect pin 43 (LDO_O) from the Phy to Pin 1 of the SOT-223 footprint WITH a 0 ohm resistor in series
    1. Populate this resistor if the MOSFET is used
  3. Connect a 0 ohm resistor from GND to Pin 1 of the SOT-223
    1. Populate this resistor if an LDO is used
    2. The LD1117S12CTR recommend a 120 ohm output load resistor to put a minimum load on the supply, please consult the LDO you select to determine if one is recommended.
    3. Could also add resistors to allow for adjustable LDO usage with additional resistor placement options
  4. Ensure sufficient heat dissipation at LDO output pin (typically > 1 inch square)

KSZ Phy Series Differences

All three of the currently available phys are generally pin-compatible with the following exceptions:

  • The "MODE" options are different between the KSZ9031 & KSZ9021 compared to the KSZ9131:
Mode 9021 9031 9131
1111 All All RESERVED
1110 All but 1000 half-duplex All but 1000 half-duplex All but 1000 Half-Duplex

As long as a PCB has provision for both pull-up and pull-down for all MODE pins on the baseboard then either of the 3 can be supported by changing the resistor values. At a minimum both a pull-up and pull-down provision should be made for the "Mode 0" bit.

  • The ISET resistor value differs between the 3 phys:
Phy ISET Resistor Value
9021 4.99k
9031 12.1k
9131 6.04k
  • Pin 14:
Phy Pin 14 Connection
9021 DVDDL (1.2V)
9031 DVDDL (1.2V)
9131 No Connect (not bonded)
  • Pin 47:
Phy Pin 47 Connection
9021 3.3V
9031 No Connect (not bonded)
9131 No Connect (not bonded)

Not bonded can actually be connected to 3.3V without harm to be compatible with 9021

  • Pin 13:
Phy Pin 13 Connection
9021 GND
9031 No Connect (not bonded)
9131 No Connect (not bonded)
  • GND Pad:

It should be noted that the GND pad MAY differ in dimensions between the KSZ phy series. The GND pad dimension is specific to the MPN selected and is not always easily identifiable in the manufacturers part number as to which size pad a particular part will have. Please review your selected footprint and solder paste stencil when using alternate Phys than the one original specified in your design.

Phy Address Latching

Depending on the IO voltage utilized for your phy you may need to have level translation between the Phy LED pins (i.e. Pin 15 and 17) and the Ethernet Jack/Activity LEDs (if used). If level translation is not done it's likely the PHY AD0 and AD1 may be latched improperly by the Phy.

Uboot and/or the kernel can be configured to auto search for Phy addresses, in the case of a single phy on the MDIO bus this means that the Phy address is not "important". However if the software is looking for a specific phy address this cause the the phy to be not found as it is setup for the wrong address.

Please see Section 9.0 of the KSZ9031 datasheet for further discussion of the Dual mode LED and Phy Address strapping pins. Below is an excerpt from the datasheet about this issue:

For 1.8V DVDDH, LED indication support requires voltage level shifters between LED[2:1] pins and LED indicator
diodes to ensure the multiplexed PHYAD[1:0] strapping pins are latched in high/low correctly. If LED indicator diodes
are not implemented, the PHYAD[1:0] strapping pins just need 10 kΩ pull-up to 1.8V DVDDH for a value of 1, and 1.0 kΩ
pull-down to ground for a value of 0.

--------------------------------------------------------------------------------------------------------------

Phy Power On Reset

The MitySOM-5CSx reference design SW incorporates a software GPIO reset during UBoot to ensure the PHY address and mode settings have been properly latched.

If this step is omitted (or there is no SW reset control) in an application care should be taken to follow the KSZ90XX datasheets recommendation for reset control, typically including a 10uF capacitor to ensure reset is de-asserted a sufficiently long enough time after power is applied. In addition one or more diodes may be used as well in this circuit. The KSZ9031 datasheet covers these use cases in section 8.0.

Kernel Support

  • Kernel 5.4 and above supports the KSZ9021, KSZ9031, and KSZ9131
  • Kernel 4.9 and below support just the KSZ9021 and KSZ9031

KSZ9131 Caveat

Critical Link has observed (correctable) packet loss after link re-establishment when using the KSZ9131 with the Arria 10's (MitySOM-A10S) HPS EMAC and suspects the same issue may be present with the Cyclone V (MitySOM-5CSx).

Symptoms

  • There is no packet loss the first time a link is established after (or during) boot.
  • If the link goes down (either via software such as ifdown or because the cable was unplugged), the SOM indefinitely fails to receive any packets after the link is re-established, and some outgoing packets are lost as well.

Workaround

Disabling advertisement of Energy-Efficient Ethernet (EEE) in the Linux device tree seems to fully resolve this issue.

In a PHY device tree node (not the MAC node), add the properties eee-broken-100tx and eee-broken-1000t. (Critical Link recommends adding both of these properties, regardless of the intended link speed.) For example:

&gmac1 {
    status = "okay";
    phy-mode = "rgmii";
    phy-handle = <&phy3>;

    max-frame-size = <3800>;

    snps,reset-delays-us = <0 10000 1000000>;
    snps,reset-gpio = <&porta 28 1>;
    snps,reset-active-low;

    mdio0 {
        compatible = "snps,dwmac-mdio";
        #address-cells = <1>;
        #size-cells = <0>;

        phy3: ethernet-phy@3 {
            /* PHY address; no autodetection when using phy-handle */
            reg = <3>;

            txd0-skew-psec = <(-700)>;
            txd1-skew-psec = <(-700)>;
            txd2-skew-psec = <(-700)>;
            txd3-skew-psec = <(-700)>;
            rxd0-skew-psec = <0>;
            rxd1-skew-psec = <0>;
            rxd2-skew-psec = <0>;
            rxd3-skew-psec = <0>;
            txen-skew-psec = <(-700)>;
            txc-skew-psec = <2400>;
            rxdv-skew-psec = <0>;
            rxc-skew-psec = <2400>;

            eee-broken-100tx;
            eee-broken-1000t;
        };
    };
};

Notable differences between this example snippet and Critical Link's reference device trees:

  • The PHY device tree node must be provided to the MAC node via the phy-handle property.
  • It seems that when using a PHY device tree node, there's no way to let Linux auto-probe for the correct PHY address (further investigation pending).
  • When using a PHY device tree node, skew values must be set directly in the PHY node, not in the MAC node.
  • The property names and encodings for skew values differ between the KSZ9131 and the KSZ9021/KSZ9031 (see Documentation/devicetree/bindings/net/micrel-ksz90x1.txt in the kernel repository)

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