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From 10/18/2013 to 11/16/2013

11/14/2013

02:39 PM FPGA Development: RE: Input/Output interfacing
Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to ...
Rich Bagdazian

11/13/2013

01:41 PM FPGA Development: RE: Input/Output interfacing
The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/image... Michael Williamson

11/12/2013

07:03 PM FPGA Development: RE: Input/Output interfacing
Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connect... Rich Bagdazian
07:01 PM FPGA Development: RE: Input/Output interfacing
Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a l...
Rich Bagdazian
05:49 PM FPGA Development: RE: Input/Output interfacing
Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported ...
Daniel Vincelette
04:47 PM FPGA Development: Input/Output interfacing
I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so t...
Rich Bagdazian

10/18/2013

12:10 PM Software Development: RE: Design examples
Right. After a little digging I figured out that QSYS does the heavy lifting of
configuring the protocol glue logic...
Rich Bagdazian
10:35 AM Software Development: RE: Design examples
I'm glad you're over the hurdle, Rich. We don't have a formal tutorial yet, other than the sample project included wi... Bob Duke
10:20 AM Software Development: RE: Moving rbf file from host to dev-board
Hi Rich,
You'll need to SCP the RBF over, I'm pretty sure FTP wasn't enabled by default. But I believe you will ne...
Daniel Vincelette
 

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