Activity
From 02/20/2014 to 03/21/2014
03/21/2014
- 06:15 PM FPGA Development: RE: Time limited SOF file question
- Hi Mike,
Never mind my last post, I found the jtag breakout board in my original shipment.
-rb
- 06:09 PM FPGA Development: RE: Time limited SOF file question
- Thanks Mike,
Makes sense. I have a Terasic USB Blaster as shown in the attached PDF file.
What's the best way to in... - 03:19 PM FPGA Development: RE: Time limited SOF file question
- Hi Rich,
This is an answer from our Altera FAE:
_You can’t create .rbf files from time limited sof files. The ... - I built a component into the FPGA that includes an instance of the Altera FIR II compiler.
At the end of the build, ...
03/20/2014
- 12:36 PM Software Development: RE: Reading memory into a file
- Hi,
Is there a way for memtool to output the memory into a file?
Thanks,
Jack
03/05/2014
- 05:24 PM Software Development: RE: Reading memory into a file
- Hi Jack,
It may take us some time to get to the bottom of this. We'll post in this thread as soon as we have addi... - 12:51 PM Software Development: RE: Reading memory into a file
- Any update on this??
03/03/2014
- 05:59 PM Software Development: RE: Reading memory into a file
- Hi Greg,
I have no problem with the software wihtout first sending the command to enable the SDRAM. The data that ... - 05:56 PM Software Development: RE: Reading memory into a file
- Hi Jack,
Do you run into any problems if you use your software without first sending the command to enable the SD... - 03:45 PM Software Development: RE: Reading memory into a file
- Hi,
I managed to read memory into a file but we got another problem.
We are following your example - write to h...
02/27/2014
- 02:40 PM Software Development: RE: Reading memory into a file
- Jack,
We don't have any general examples to provide.
If you're trying to share data over FTP or ssh in a human... - Hi,
Do you have any examples on reading memory in software?
We need to grab the data we have in memory into a f...
02/22/2014
- 07:48 AM Software Development: RE: Yocto Plug-In Python.exe Error
- Can you post a capture of your complete shell interaction?
02/20/2014
- 02:39 PM FPGA Development: RE: HPS Memory Controller
- Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS read...
- 01:10 PM FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Th... - 01:03 PM FPGA Development: RE: HPS Memory Controller
- At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. ...
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