Activity
From 07/06/2016 to 08/04/2016
08/03/2016
- JK 03:27 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I proceeded to try to use Yocto to build the Altera 4.1.22 LTSI RT kernel based on your suggestions above.
Unfortunately, the compilation of the kernel is erroring out because of an incompatible GCC version. The followin...
08/02/2016
- DV 11:55 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Jared,
That sounds like a perfect approach. For building the file system we do use yocto, which as you saw is pointed to use the 3.16 kernel. Now depending on how manual you want to do this I can suggest a few options.
Probab... - JK 10:26 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I've been going through the instructions on the Wiki to get an SD card image of my creation working. I'm starting with the 3.16 kernel version provided by Critical Link to get a handle on the process of building an SD card ...
07/29/2016
- DV 03:01 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Jared,
I did a quick test here and was able to boot altera's 4.1.22 ltsi rt kernel using the MitySOM-5CSX dev kit. I used the socfpga_defconfig and socfpga_cyclone5_sockit.dts. I didn't do an extensive test but was able to boot ...
07/28/2016
- Context: My company recently purchased some MitySOM 5CSX Development Boards and would like to use them on a current project. This project likely has the need for a real-time operating system. I want to start by using Linux with the PREEM...
07/11/2016
- AD 09:41 AM FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Tom,
As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPGA I/O. A bank 8A pin is acceptable.
- Adam - TC 09:02 AM FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fine.
Thanks,
Tom. - TC 08:37 AM FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Adam,
Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO can be used.
Would HPS_GPIO44 (pin244 on the MitySOM) be usable if I set up HPS loaning for that pin so that the FPGA c... - AD 08:11 AM FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Thomas,
The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures the FPGA over the PCI Express bus interface. To use this mode, the PERSTN has only one option for the pin location. For...
07/09/2016
- Hi,
We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently going over the pin mappings to make sure that we have enough pins.
I was reading through the design guide for the boar...
07/07/2016
- DV 11:26 AM Software Development: RE: /sys/class/fpga-bridge directory is empty
- Thank you for letting us know about this, it was a bug that was caused by some updates to the ethernet driver, which in turn caused some changes in the dtsi. I've pushed the fix to our git repo, it converts how the reset manager was inte...