Activity
From 10/20/2025 to 11/18/2025
10/22/2025
- 01:46 PM FPGA Development: RE: Building the MitySOM-5CSX
- John,
Taking a look at your output it appears like you successfully recompiled the SPL and UBOOT. The differences ... - 02:19 AM FPGA Development: RE: Building the MitySOM-5CSX
- Hi, so I was able to make uboot and an sd card image. I took the image and loaded it to a blank sd card and powered ...
10/21/2025
- 06:55 AM FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance
- Hi Mike,
Thanks for your quick reply.
Here’s what I’ve tried and what I’m seeing:
Reseated the SOM in the DIMM ... - 12:32 AM FPGA Development: RE: Building the MitySOM-5CSX
- Mike,
Thanks. Understood.
Regards,
John
10/20/2025
- 04:26 PM FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance
- Hi Atef,
It sounds like based on your findings the SOM module is the issue. It looks like you may have tried to re... - 03:41 PM FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance
- [https://res.public.onecdn.static.microsoft/assets/mail/file-icon/v2/photo_16x16.png]1000008159.jpg<https://sascaila...
- 03:03 PM FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance
- Hi Atef,
Thank you for the thorough debug details.
# Have you successfully used this development kit before? Or... - Hello Critical Link Support,
I’m evaluating a MitySOM-5CSX module (part number 5CSX-H6-42A-RI) and I’m trying to r... - 02:08 PM FPGA Development: RE: Building the MitySOM-5CSX
- John,
For some background, we have a single Quartus reference design project we have setup for the Cyclone V platf...
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