Activity
From 11/14/2025 to 12/13/2025
12/09/2025
- DV 02:54 PM FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hi Atef,
You should be able to do this via ethtool: - AF 02:50 PM FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hi Zach,
Could you please generate a Linux image for the 5CSX-H6-4YA based on the Linux image available at the following link (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki), but configured so that the Ethernet li... - MW 10:25 AM FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hello,
For layout, the two groups you have outlined in your schematic snippet should be matched in length and ideally be on the same layer. The clocks should be separated from the data lanes by at least 5x trace width. We usually ... - AF 08:47 AM FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hi Zach,
Just a quick update on my side.
I am now able to communicate over Ethernet with our custom carrier board. However, in some cases I still observe data loss that results in dropped connections. My current suspicion is that thi... - AF 08:15 AM FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hi Zach,
Thank you for your reply.
I ran ethtool eth0 | grep PHYAD on my system, and it confirms that the PHY is detected at address 3, as shown in the attached screenshot.
Could you please let me know if the Ethernet hardware section...
12/08/2025
- ZM 05:40 PM FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hi Atef,
The image you downloaded should have an SSH server (OpenSSH) running by default, yes. @ps@ by default doesn't show all processes, which is why the grep in your screenshot didn't find it. Running @ps -A@ or @ps aux@ should con... - Hello,
I am working with a MitySOM-5CSx module on my own custom carrier board and I am seeing different behavior depending on which SD card image I use. I would appreciate your help to understand the correct configuration.
+*Hardware...
12/02/2025
- AF 12:47 PM FPGA Development: RE: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board
- Thanks, it works.
12/01/2025
- MF 04:20 PM FPGA Development: RE: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board
- Atef,
Can you make sure you have the MSEL set appropriately per the table below?
!image.png! - Hello,
I am trying to test bitstream encryption on a MitySOM-5CSx evaluation board and I am running into an issue during boot.
Here is what I have done so far:
In Quartus, I enabled bitstream encryption and generated an encrypted RBF ...
11/28/2025
- AF 03:57 PM FPGA Development: RE: Using the design security for MitySOM-5CSX
- Hello,
I would like to encrypt the FPGA bitstream on the MitySOM-5CSX. I have been referring to Intel’s application note AN557 (Using the Design Security Features in Intel FPGAs) to understand how to enable bitstream (.rbf file) encrypt...
11/19/2025
- JI 12:43 PM FPGA Development: RE: Building the MitySOM-5CSX
- Seth,
I got the GPIO pin on the FPGA side to work as you described. This is just as good as having an LED because the whole point was to have an example to study how the GPIO is triggered from the linux side,i.e. how the command "worms...
11/14/2025
- MF 08:59 PM FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
Okay that makes sense! In that case, I would look into Arm Developer Studio then. You should be able to obtain an evaluation license and it should be able to accomplish what you are asking for. There are potential open-source so... - AF 08:50 PM FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Mike,
Thank you for your response, I’ll have a look at it.
I was focusing on using JTAG because I’m having an issue with SD-card boot on the carrier board I designed.
Thanks again for your help. - MF 04:03 PM FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
If you see our Wiki page here: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki we post full SD card images for the development kits. These SD cards will use U-Boot as the bootloader which the HPS loads first t... - AF 03:50 PM FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Mike, Thanks for your response. Yes, I was trying to load the compiled C code binary directly to the HPS via JTAG. Since there is no tutorial available for that method, could you please send me (or point me to) your tutorial explaining h...
- MF 03:42 PM FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
Glad to hear you resolved your JTAG issue. Can you elaborate on how you are trying to load the HPS portion? Are you trying to load binaries directly to the HPS via JTAG? Unfortunately we do not have any tutorials at the moment t... - AF 10:31 AM FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Thank you Mike, the system works by reversing the USB Blaster connection. I have another question please: Do you have a tutorial that explains how to load the HPS portion using WSL on Windows? Thanks.