Activity
From 01/30/2026 to 02/28/2026
02/27/2026
- DV 08:18 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Are you using the "Makefile":https://support.criticallink.com/gitweb/?p=mitysom-5csx-ref.git;a=blob;f=dev_5csx_h6_42a/Makefile;h=7d61fe6112ad18bf792a770dd3a5721078b5c475;hb=refs/heads/23.1-stable at the top of the FPGA proje... - XS 07:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your support, I build a envirment with Ubuntu 22.04 and Quartus 23.1; and finish re-build uboot. But when i try to generate SD image file, I got below:
$ make sd_image
scripts/kconfig/conf --synccon...
02/23/2026
- DV 08:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Boot *Makefile* (around line 40), *or* it could be related to your build environment: it looks like you're using our Ubunt... - XS 07:03 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang
02/09/2026
- XS 03:49 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
BR,
Xiang
02/06/2026
- DV 10:17 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following: - XS 09:11 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defconfig
Makefile:40: *** missing separator. Stop
what can I do?
BR,
Xiang
02/05/2026
- DV 09:42 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually change it. Here are our build instructions for the preloader and u-boot: https://support.criticallink.com/redmine/projects/mi... - XS 09:04 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot. Could you give me a detail instruction ? Thanks!
BR,
Xiang
02/03/2026
- XS 04:42 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boot to try again.
- DV 04:11 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because the preloader also enables the bridges as part of configuring the HPS I/Os. Because of this, the correct and supported p...
- DV 03:58 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would like. Here is the HPS doc on the FPGA port controller register map: https://www.intel.com/content/www/us/en/programmable... - XS 02:36 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can do release these bridges out of reset? Now, I can use Putty connect system by SSH.
BR,
Xiang
02/02/2026
- DV 09:59 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is needed because the HPS is the one that takes these bridges out of reset.
Best regards,
Dan - Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_master to read out the data from HPS DDR, but always timeout. Need a bridge or something worng?
clipboard-20260202...